Aman Rastogi

Product Manager

Greater Delhi, India11 yrs 9 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

Expert in memory compiler development and validation.
Proficient in PCIe and automotive protocol design.
Strong background in training and project management.

Stackforce AI infers this person is a Semiconductor Engineer with expertise in memory design and protocol development.

Contact

Skills

Core Skills

PcieProject ManagementMemory Compiler DevelopmentLeafcell DevelopmentIr Drop AnalysisDfm

Other Skills

10g ethernetASICAlgorithmsAnalog Circuit DesignArtificial Neural NetworksAutomationCC++CMOSCadence VirtuosoCircuit DesignCode ReviewData StructuresEDAFDSOI Technology

About

There is nothing that can't be accomplished without effort. Always strive towards the end goal, with patience and perseverance.

Experience

Logic-fruit technologies pvt ltd

R & D Engineer

May 2016 – Present · 9 yrs 10 mos · Gurgaon, India

Working here as a module lead presently.
Currently working in the PCIe domain.
Major responsibilities being as follows :
1) Responsible for all the job assignment of assigned project.
2) Proper effort estimation of the project.
3) Meet project time lines and willingness to stretch when required.
4) Ensure good quality and proper code review for the project.
5) Training R&D Engineers.
Have worked on the following protocols :
1) PCIe
2) 10g ethernet
3) LIN,Flexray (Automotive protocols)
4) HSR-PRP

PCIe10g ethernetLINFlexrayProject ManagementCode Review+1

Stmicroelectronics

Design Engineer

Jul 2014 – May 2016 · 1 yr 10 mos · Greater Noida

Worked as a design engineer in the memories team(SMEM) of the TRnD(Technology Research and Development) group.
Main task being to develop and support back end product for memory compiler.
Key responsibilities include leafcell development,memory validation,product support and test chip,process adherence and basic automation.
Major Project:
Worked on a fresh memory compiler development in FDSOI technology. Compiler titled SPSMHD and designated as a single port,high density compiler with major focus on area reduction and regularity.
Activities and key responsibilities:
1. Leafcell development of the control part of the memory compiler. Main responsibilities being ownership of the control block,full layout development of the leafcell,considering specs,DRC(Design Rule Check),LVS(Layout Vs Schematic),SRD(Structurally Regular Design),DFM(Design for manufacturability),anticipating electromigration and IR drop.Extrememly high focus on regularity.
2.Leafcell extraction(Corners,methodology,need and contents of the spice files).Leafcell abutment,full memory cut level validations.
3.Awareness about the signal flow in memory compiler and other design contraints which impacts the layout.
4.Resposible for pre design analysis of bank architecture possibilities.
Minor Project related activities:
1.Analyzing the IR drop in a ROM compiler and reducing the drop to the desired threshold.
2.DFM(Design for manufacturability) related updates in memory compilers like SPHD _LOLEAK,ROM_LOLEAK and DPHD_LOLEAK compilers. DFM related updates cater to improving the yield. Also partook in some minor design related changes in the above mentioned memory compilers.
3.Test chip abstract change in some compilers.
4.Testing of new design methodologies and automations.