Anand Illa

CEO

Bengaluru, Karnataka, India23 yrs 2 mos experience

Highly Stable

Key Highlights

Led design teams for 5 generations of Data Center products.
Built and retained high-performing teams across functions.
Achieved PPA improvements through strategic collaborations.

Stackforce AI infers this person is a leader in semiconductor design and engineering, specializing in SOC and physical design.

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Skills

Core Skills

Physical DesignCollaborationSoc Sd ExecutionSchedule ManagementTest Chip ExecutionFull Chip IntegrationPhysical IntegrationEdaFull Chip Layout ConvergenceCustom Layout DesignFull Chip Integration MethodologyPhysical ConvergenceIp Coordination

Other Skills

PPA improvementsEngineering executionBusiness acumenQuality managementGoal settingDependency managementRTL DesignValidationPower deliveryTape OutDesign stylesProductivity solutionsLayout productivity solutionsDFMLayout Productivity scripts

About

Efficient and Quality Design Implementation across wide range of Products (Clients, Servers), IPs (Telco/Networking, Graphics, CPU) and Foundry technologies Technology Leader: Leading physical design teams on work load specific optimization of products, PPA enrichment of critical IPs, process technologies o Data Center: Intel Xeon vRAN (Telco Network) and Intel Xeon Max (Memory) [Total: 5 generations of DC products] o Clients: Nextgen Desktop and Nextgen AI PC [Total: 8 generations of clients products and associated test chips] Dynamic Leader: visionary in hiring, building teams and retaining talent. Impeccable record of leading teams across functions and domains delivering to business goals Effective collaborator: Consistently delivered business results in matrix organized structure through culture of collaboration between teams and customers/ecosystem partners

Experience

23 yrs 2 mos

Total Experience

23 yrs 2 mos

Average Tenure

23 yrs 2 mos

Current Experience

Intel corporation

7 roles

Sr Director (SOC Design)

Promoted

Sep 2020 – Present · 5 yrs 7 mos

Unique mix of precise engineering execution and business acumen
Leading Physical design team for Networking, Edge and Client products
Collaborate with stakeholders – IP’s, other SOC’s, technology and EDA
Drive PPA improvements throughout the design cycle by partnering with Technology providers, EDA vendors

Physical DesignCollaborationPPA improvementsEngineering executionBusiness acumen

Director (SOC Design)

Oct 2016 – Sep 2020 · 3 yrs 11 mos

Drive SOC SD execution with laser sharp focus on schedule and quality. Setting the right goals, priorities and managing dependencies with all input teams (RTL, HIP and TFM among others). Tracking execution progress daily and making priority calls -- this is across all domains of SD implementation from Floorplan, Synthesis, PNR and all vectors of Convergence. Setup processes for execution and define guard rails for each partition lead to drive implementation of their partitions

SOC SD executionSchedule managementQuality managementGoal settingDependency management

Engineering Manager

Apr 2014 – Oct 2016 · 2 yrs 6 mos

Built Intel India’s 22FFL Test Chip execution team (RTL Design, Validation and SD)
Partnering to develop IP-ECO system (with right KPI’s) for products execution
Managing team responsible for Full chip Floorplan, Structural Design, SOC-IP
Full chip Integration, clocking, power delivery, Full Chip Timing & EDA for couple of server products

Test Chip executionRTL DesignValidationFull chip integrationPower delivery

Engineering Manager

Apr 2010 – Apr 2014 · 4 yrs

Products: Xeon-D, Xeon Broadwell SOC's; Core and GT-HIPs (Ivybridge, Skylake, Cannonlake)
Managing team responsible for Full chip physical integration (incl. EDA) and Tape Out
Driving physical convergence across design styles [Full Chip, P&R Designs, Custom
layout, Memories]
Efficient Derivative development (lowest engineering effort for subsequent dies from
the base die)
Analog (Custom), Memory Layout Automation, Productivity solutions and
Methodologies
Enhancing SoC solutions to cater to the high frequency needs of Core I products

Physical integrationEDATape OutDesign stylesProductivity solutions

Engineering Manager

Promoted

Apr 2008 – Apr 2010 · 2 yrs

Products: Westmere-EX, EP; Core & GT-IP's (Haswell, Ivybridge)
Full chip layout convergence, Metal fill solutions, Custom layout design methodologies,
Layout productivity solutions, Tape In
Largest die in the world in terms of transistor count at that time
Building team for future projects

Full chip layout convergenceCustom layout designLayout productivity solutions

Senior Design Engineer

Promoted

Apr 2005 – Apr 2008 · 3 yrs

Product: Dunnington (45nm Server)
Full Chip Integration methodology and execution
Custom Layout Design Methodologies, DFM, Layout Productivity scripts
Full Chip DFM, FCL convergence, Indicators, Tape-In
Largest die in the world in terms of transistor count at that time

Full Chip Integration methodologyCustom Layout DesignDFMLayout Productivity scripts

Design Automation Engineer

Feb 2003 – Apr 2005 · 2 yrs 2 mos

Single handedly drove entire physical convergence and TapeIn of one die
IP Coordination, Feedback to IP design on quality criteria and assisting them in
convergence
Full Chip Integration and Mock TI’s
Fub Layout Design Methodologies, DFM, Layout Productivity scripts
P&R DFM, Physical Design Tools support, Library Design, Memory design

Physical convergenceIP CoordinationLibrary DesignMemory design