Deepak Namana

Software Engineer

Andhra Pradesh, India9 yrs 10 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

Expert in Physical Design and VLSI methodologies
Experience with advanced technology nodes like TSMC N5 and N7
Proven track record in managing complex chip-level designs

Stackforce AI infers this person is a VLSI Design Engineer specializing in Physical Design for advanced semiconductor technologies.

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Skills

Core Skills

System On A Chip (soc)Physical DesignVlsi

Other Skills

Clock Tree SynthesisDesign Rule Checking (DRC)FloorplanningPlace & RouteTiming ClosureStatic Timing AnalysisCadence EncounterMicrosoft OfficePowerPointManagementMicrosoft WordVery-Large-Scale Integration (VLSI)

About

CAREER OBJECTIVE Looking forward to work on challenging tasks where I can put my skills to maximum use and sharpen my capabilities that help me achieve personal as well as organization goals. PROFESSIONAL SUMMARY ▪ Worked on N5, N7, 28nm, TSMC 40nm, TSMC 90nm and 130nm technology nodes. ▪ Handled partitions with instance count ~2.8M. These partitions go into complex networking subsystem RDMA. These are congestion, LOL & Fanout critical partitions. ▪ Handled CPU partition which has Cadence Xtensa core and runs at 1.2GHz @ 0.675V ▪ Worked on chip level activities which includes IO & Bump placement and Analog custom routings. ▪ Dealt with blocks having floorplan critical & routing congestion and Clock Tree Balancing issues. ▪ Responsibilities were doing sanity checks, floor planning, placement issues, balancing clock tree based on timing issue, routing issues, STA, EMIR and LV checks. SKILS ▪ Tools: Fusion Compiler, ICCII, ICC & PT. ▪ Scripting Languages: TCL

Experience

9 yrs 10 mos

Total Experience

1 yr 11 mos

Average Tenure

3 yrs 10 mos

Current Experience

Intel corporation

SoC Design Engineer

Jun 2022 – Present · 3 yrs 10 mos · Bengaluru, Karnataka, India · Hybrid

➢ Responsible for partitions which goes into complex networking subsystem RDMA.
➢ Worked on partitions in TSMC N5 technology node which go into 2nd generation of IPU.
➢ Worked on partition which goes into 1st generation of IPU in TSMC N7 technology node.
➢ Responsible for complete partition Implementation which includes PnR, STA, Physical Verification & EMIR

Physical DesignClock Tree SynthesisSystem on a Chip (SoC)

Infineon technologies

Staff Engineer

Feb 2019 – May 2022 · 3 yrs 3 mos · Bengaluru, Karnataka, India · On-site

➢ Responsible for Full chip design (Digital on Top) which is Analog IP dominated. These are mostly on 90nm & 130nm technology nodes.
➢ Worked on chip level activities which includes IO & Bump placement and Analog routings.
➢ Also responsible for PnR execution for these chips including Physical Verification.
➢ Worked on block level PnR as well which are 45nm & 28nm technology nodes. Responsible for complete Synthesis & PnR execution including Physical Verification.

Design Rule Checking (DRC)FloorplanningPhysical DesignVLSI

Aranis business process services pvt ltd

Design Engineer

Feb 2018 – Feb 2019 · 1 yr · Bengaluru, Karnataka, India · On-site

Worked for client Infineon Technologies.
➢ Responsible for Full chip design (Digital on Top) which is Analog IP dominated. These are mostly on 90nm & 130nm technology nodes
➢ Worked on chip level activities which includes IO & Bump placement and Analog routings.
➢ Also responsible for PnR execution for these chips including Physical Verification

FloorplanningDesign Rule Checking (DRC)Physical DesignVLSI