Gutlapalli Swaroopa — DevOps Engineer
Working as a Design Verification Engineer with strong expertise in SystemVerilog (SV) and UVM methodologies, focused on SoC design verification. I am proficient in industry-standard tools such as VCS and Verdi for simulation, debugging, and waveform analysis. My strengths include identifying complex bugs, root-cause analysis, and improving testbench efficiency to achieve better coverage.
Stackforce AI infers this person is a Design Verification Engineer specializing in SoC design verification and embedded systems.
Experience: 2 yrs 9 mos
Skills
- Systemverilog
- Universal Verification Methodology (uvm)
- Embedded Systems
Career Highlights
- Expert in SystemVerilog and UVM methodologies.
- Proficient in VCS and Verdi for simulation and debugging.
- Strong background in embedded systems and control card development.
Work Experience
Intel Corporation
SOC Design Verification Engineer (1 yr 9 mos)
MEDHA SERVO DRIVES PVT LTD (MSDPL)
Research And Development Engineer (1 yr)
Education
MTech at National Institute of Technology, Tiruchirappalli
Bachelor of Technology - BTech at Sree vidyanikethan engineering college
Intermediate at Sri Chaitanya Junior College
SSC at SSS EM SCHOOL
