N

Naveen Rashinkar

Software Engineer

Bengaluru, Karnataka, India12 yrs 5 mos experience
Most Likely To SwitchHighly Stable

Key Highlights

  • Expert in physical design for advanced technology nodes.
  • Strong background in static timing analysis and verification.
  • Proficient in developing and maintaining design flows.
Stackforce AI infers this person is a Semiconductor Physical Design Engineer with expertise in advanced technology nodes.

Contact

LinkedIn

Skills

Core Skills

Physical DesignStatic Timing Analysis

Other Skills

Physical VerificationCMOS TechnologyFloor PlanPower PlanPlacementCTSRoutingScripting LanguagesSynopsys IC CompilerDesign CompilerDigital DesignsVerilogRTL designRTL verificationLogic Synthesis

About

Experience in Top & Block Implementation in 28, 22, 16, 14, 7 nm tech nodes using Innovus, ICC & ICC2 which include Floor planning, Power plan, Placement, CTS, Opt, Routing and Physical Verification.Experience in develop, support & maintain physical design flows and methodologies.Sound knowledge in static timing analysis, Physical verification and CMOS technology.

Experience

12 yrs 5 mos
Total Experience
6 yrs 2 mos
Average Tenure
9 yrs 11 mos
Current Experience

Mediatek

4 roles

Senior Staff Engineer

Promoted

Jun 2023 – Present · 2 yrs 10 mos

Staff Engineer

Jun 2020 – May 2023 · 2 yrs 11 mos

Senior Design Engineer

Promoted

Jan 2018 – May 2020 · 2 yrs 4 mos

Design Engineer 2

Mar 2016 – Jan 2018 · 1 yr 10 mos

Infineon technologies

Physical Design Engineer

Aug 2013 – Feb 2016 · 2 yrs 6 mos · Bangalore

  • Comprehensive knowledge of physical design implementation and strategies.
  • Worked on 40nm, 65nm technology node designs.
  • Sound knowledge in static timing analysis, Physical verification and CMOS technology.
  • Worked on MCMM, UPF and TPNS based designs at different technology nodes.
  • Expertise in Floor Plan, Power Plan, Placement, CTS and Routing.
  • Experience in develop, support & maintain physical design flows & methodologies
  • Good Knowledge in scripting languages like shell, PERL, TCL.
  • Expertise in using Synopsys IC Compiler, Design Compiler tools
Physical DesignStatic Timing AnalysisPhysical VerificationCMOS TechnologyFloor PlanPower Plan+6

Education

Sri Jayachamarajendra College of Engineering

Master of Technology (MTech) — VLSI Design and Embedded System

Jan 2012 – Jan 2014

RV-VLSI Design Center

Advanced Diploma in ASIC Design

Jan 2011 – Jan 2012

East West Institute of Technology

Bachelor's degree — Electronics & Communications

Jan 2007 – Jan 2011

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