MELDIYA THOMAS

Software Engineer

Bengaluru, Karnataka, India9 yrs 6 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

Expert in ASIC Physical Design and VLSI methodologies.
Proficient in EDA tools like Cadence INNOVUS and Synopsys ICC2.
Strong scripting skills in Perl and TCL for automation.

Stackforce AI infers this person is a VLSI Design Engineer with expertise in ASIC and Physical Design.

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Skills

Core Skills

Physical DesignStatic Timing AnalysisAsic Physical Design

Other Skills

Very-Large-Scale Integration (VLSI)Power PlansDesign Rule Checking (DRC)Layout Versus Schematic (LVS)Clock Tree Synthesis (CTS)ASIC flowFloorplanningPower PlanningClock Tree SynthesisTiming ClosureTCL scriptingTweakerERCSystem on a Chip (SoC)Application-Specific Integrated Circuits (ASIC)

About

Career Objective: Seeking a challenging job in the field of VLSI design/Physical Design Hands on experience on EDA tool Cadence INNOVUS, Synopsys IC Compiler/ICC2, Prime Time,Design Compiler. Scripting Languages : Perl , Tcl , shell Interested Field : ASIC Physical Design

Experience

9 yrs 6 mos

Total Experience

2 yrs 4 mos

Average Tenure

4 yrs 4 mos

Current Experience

Mediatek

Senior Physical Design Engineer

Dec 2021 – Present · 4 yrs 4 mos · Bengaluru, Karnataka, India

Physical DesignStatic Timing AnalysisVery-Large-Scale Integration (VLSI)Power PlansDesign Rule Checking (DRC)Layout Versus Schematic (LVS)+1

Qualcomm

Physical Design Engineer

Apr 2018 – Dec 2021 · 3 yrs 8 mos · Banglore

Physical Design Engineer at Qualcomm (contract base) through Si2chip Technologies and pvt

Physical DesignVery-Large-Scale Integration (VLSI)

Si2chip technologies pvt. ltd.

Associate Design Engineer

Mar 2017 – Mar 2018 · 1 yr · Bengaluru, Karnataka, India

Rv-vlsi vlsi and embedded systems design center

Physical Design Engineer Trainee

Jul 2016 – Jan 2017 · 6 mos · Bengaluru Area, India

Trained as a Physical Design Engineer and implemented ASIC flow (netlist to GDSii) at block level with critical power, area and timing budgets. Designed floor-plans with high macro count and power-planned with strict IR drops and power budgets. Synthesized clock tree (CTS) while meeting targets like max skew and min/max insertion delay. Generated and analyzed timing reports of per-layout and post-layout STA on PrimeTime with OCV and Xtalk, and resolved timing violations. Optimized the design for multiple modes and multiple corners (MCMM). Performed timing closure on technologies with aggressive timing and power budget. Worked on DFT related concepts like scan-chains and performed re-ordering to optimize it.Currently working on Linux and automated various analysis and violation fixes by writing TCL scripts.

ASIC flowFloorplanningPower PlanningClock Tree SynthesisTiming ClosureTCL scripting+2