Lakku Rajiv Reddy — Director of Engineering
Specialties: ASIC Verification HDL's : Verilog, VHDL HVL's : Specman (e), System Verilog Methodologies: eRM,UVM Gatesimulation Scripting: Perl/Shell. Functional Qualification Using Certitude EDA Tools: Cadence Tools(ncverilog,irun),Specman-Elite,eManager(ePlanner),Xilinx ISE,Modelsim
Stackforce AI infers this person is a highly skilled ASIC Verification Engineer with expertise in EDA tools and methodologies.
Location: Bengaluru, Karnataka, India
Experience: 19 yrs 3 mos
Skills
- Asic Verification
- Functional Verification
Career Highlights
- Expert in ASIC Verification methodologies.
- Proficient in multiple HDL and HVL languages.
- Strong background in EDA tools and functional verification.
Work Experience
Intel Corporation
SOC Design Verification Lead (4 yrs 5 mos)
Altran
Technical Unit Manager (1 yr 2 mos)
Team Manager (3 yrs 8 mos)
HCL Technologies
Technical Lead (3 yrs 7 mos)
Sr.Member Technical Staff (2 yrs 8 mos)
Member Technical Staff (3 yrs 8 mos)
Education
M.Tech at College Of Engineering, Pune
B.Tech at Sri Venkateswara University
