Satish U — DevOps Engineer

• Having 4+ years strong Experience in IP and subsystem verification. • Test Bench Architecture And Environment Development and debugging skills. • Verifying Design at subsystem level, IP level, and block level, able to write sequences, checkers, scoreboards and tests for complex verification • Feature Plan, Test Plan, Checker Plan, Coverage Plan, And Feature To Test Mapping • Sanity And Regression Clean-Up. • Function/Code Coverage Development And Closure • full testbench setup migration from ncsim to VCS. Have Ramp up team members Protocol : Ethernet, AMBA AXI4, AHB, Sonet/SDH, APB, I2C, SPI Code coverage and Functional coverage , Assertions TLM1 Hands on debugging Tools : VCS, QuestaSim and Cadence. NCSIM Languages : System Verilog, Verilog, C, Methodology : UVM. scripting: Pearl

Stackforce AI infers this person is a skilled verification engineer in the semiconductor industry.

Location: Bengaluru, Karnataka, India

Experience: 6 yrs 7 mos