PREM DEEP VERMA — DevOps Engineer
7+ Years of Experience in Design verification, Testbench development, Assertion, Constraints, Coverage analysis and Debugging. ================================= Specialties in Design Verification Domain ================================= IP Verification : DDR-PHY, DDR4, DDR5, LPDDR2, LPDDR4, LPDDR5,LPDDR5X,LPDDR5Y,LPDDR5Z Bus Protocols : APB, AHB, AXI, I2C, SPI HVL: System Verilog HDL: Verilog Methodology: UVM Scripting Language: Linux , Python Simulations: RTL Simulation, GLS Simulation, Power Aware Simulation
Stackforce AI infers this person is a Design Verification Engineer with expertise in VLSI and memory protocols.
Location: Bengaluru, Karnataka, India
Experience: 7 yrs 8 mos
Career Highlights
- 7+ years in design verification and testbench development.
- Expertise in multiple memory protocols including DDR and LPDDR.
- Proficient in System Verilog and UVM methodologies.
Work Experience
Qualcomm
Senior Lead Verification Engineer (1 yr 3 mos)
Senior Design Verification Engineer (2 yrs 9 mos)
Xilinx
Design Verification Engineer II (1 yr 7 mos)
Design Verification Engineer (2 yrs)
Education
Master of Technology - MTech at National Institute of Technology Agartala
Bachelor of Engineering - BE at Rajiv Gandhi Prodyogiki Vishwavidyalaya
XII at Central Board of Secondary Education
X at Central Board of Secondary Education
