Raj Jadhav — Product Engineer
Design and implementation of Block level PNR flow from Synthesis to Signoff. The flow included Floorplan, Powerplan, Placement, CTS, Routing and all other signoff considerations. Efficient in timing closure at block level as well as chip level at signoff stage.
Stackforce AI infers this person is a Semiconductor Design Engineer with expertise in Physical Design and Timing Analysis.
Location: Bengaluru, Karnataka, India
Experience: 5 yrs 6 mos
Skills
- Physical Design
- Static Timing Analysis
Career Highlights
- Expert in block-level PNR flow from Synthesis to Signoff.
- Proficient in timing closure at both block and chip levels.
- Hands-on experience with Synopsys tools for VLSI design.
Work Experience
Intel Corporation
EDA tools hardware engineer (1 yr 2 mos)
AppEx Semiconductor Pvt Ltd
Physical Design Engineer (3 mos)
LeadSoc Technologies Pvt Ltd
Physical Design Engineer (3 mos)
Intel Corporation
Physical Design Engineer (3 yrs 2 mos)
RV-VLSI VLSI and Embedded Systems Design Center
Trainee at RV-VLSI (8 mos)
Education
BE - Bachelor of Engineering at Pillai College of Engineering
