Prabhu Manjunath

Director of Engineering

Bengaluru, Karnataka, India24 yrs 5 mos experience

Highly Stable

Key Highlights

25 years of experience in Design and Verification.
Led high-performance teams delivering successful CPU & GPU products.
Strong expertise in RISC-V, ARM, and Intel Architectures.

Stackforce AI infers this person is a Semiconductor Engineering Leader with extensive experience in CPU and GPU verification.

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Skills

Other Skills

ASICFunctional VerificationVerilogSystemVerilogEmbedded SystemsComputer ArchitectureFormal VerificationSpecmanIntelStatic Timing AnalysisMicroprocessorsVLSIRTL DesignDebuggingSemiconductors

About

A Design and Verification professional with a 25 year track record of delivering towards multiple high quality compute, graphics & SoC products at multiple product based organizations. A result oriented technical manager, with broad experience across different levels of verification, including unit level, cluster level and full chip verification of CPU’s, GPU's and SoC's - from planning stage to tape-out. Strong background in RISC-V, ARM and Intel Architectures and various Processor Micro-Architectures. I currently head the DV charter for Mediatek India. Experience in building highly motivated and impactful teams and driving them towards organizational goals. Handling stake holders across design centers and geographies. I have lead large high performance teams, which have consistently met or exceeded expectations to deliver highly successful CPU & GPU products at large organizations. An effective communicator, coach and guide. Aptitude to learn and experiment with new technologies and areas. Willingness to adapt. Comfortable working with ambiguity. #CPU, #GPU , Design Verification, Performance , RISC-V, ARM, Intel IA32, Cache Coherency, Memory Subsystem, Memory Management Unit and Translation, Team Building, Innovation.

Experience

24 yrs 5 mos

Total Experience

3 yrs 10 mos

Average Tenure

1 yr 3 mos

Current Experience

Mediatek

Senior Director

Jan 2025 – Present · 1 yr 3 mos

Lead the Design Verification team for Mediatek India.

Intel corporation

Director Of Engineering

Aug 2021 – Jan 2025 · 3 yrs 5 mos

Led the Performance Validation of GPU's & High Throughput Computing Devices at Intel
Responsible for the performance validation of all 3 lines of Graphics IP's from Intel ( Low Power Integrated Graphics , Discrete Graphics and High Performance Compute/Data-Centre GPU).
My team was responsible for the Performance Verification & Perf Improvements of many notable IP/products from Intel, including Intel Core Ultra series (Meteor Lake, Lunar Lake & Panther Lake) , Intel ARC A&B series Discrete GPU's , Intel Ponte Vecchio (PVC) - For Data Centre GPU's.

Western digital

Director, R&D Engineering

Aug 2019 – Aug 2021 · 2 yrs · Bengaluru Area, India

Led the CTO RISC-V R&D Engineering team in India . Responsible for verification of all inhouse RISC-V CPU's from Western Digital - SweRV series CPU's

Arm

3 roles

Senior Manager

Jul 2016 – Aug 2019 · 3 yrs 1 mo

Led the Verification Team responsible for Top Level Verification of the first Multi-Threaded Arm CPU, the Arm Neoverse E1 processor and its automotive Automotive Enhanced variant Cortex A65-AE, with Split and Lock Step functionality. Included all aspects of verification planning, resourcing, execution & tracking , including stakeholder management across multiple geographies.
Site lead for Functional Safety ( FuSa ) aspects of Top DV verification for all CPU’s verified at the Bangalore center.

Manager

Promoted

Jun 2012 – Jun 2016 · 4 yrs

Led the Verification Team responsible for Top Level Verification of ARM Cortex A53 processor ( Apollo ) - the first 64 Bit low power processor based on ARM's v8 Architecture. Cortex A53 is also one of the most widely used A-class ARM processor.
Handled the verification planning, resourcing, execution and delivery of Arm Cortex-A53 CPU under tight schedules with multiple customer configurations.

Technical Lead

Oct 2010 – May 2012 · 1 yr 7 mos

Lead Engineer - Architecture Verification of Memory Virtulization verification suites for the new 64 bit ARM v8 Architecture. Responsible for all aspects of the delivery of v8 Mem Virtualization Architectural Verification Suites.
Lead developer for the Page Table Generator tool used for Static Page Table generation in all of the v8 verification suites by ARM.

Intel

Senior Engineer

Sep 2004 – Oct 2010 · 6 yrs 1 mo · India

Verification of L2 Cache Controller, Coherency Engine, Bus Cluster & Memory Subsystems of Multiple Server Class Xeon CPUs at Intel. Part of the team that built the first CPU from India, codename Dunnington. Verification at Unit and Cluster Level - constrained random stimulus using Specman 'e' based testbench. Coverage Driven Verification.