Kalpana Verma — Product Engineer
Working as a DFT Engineer since december 2021, at MediaTek BANGALORE. I have an experience on ATPG, Compression, IJTAG, Tetramax2, Tessent TK, SCAN, Synopsys tool, Verdi, Xcelium simulator. VCS Simulation, Post Silicon. Understanding of verilog commands, VHDL. Done 4 tapeouts. for smart Mobile Soc. Worked on SSN projects. DFT training From ChipEdge Technologies Pvt. Ltd. Actively Seeking for a full time Job Opportunity in VLSI Domain as a DFT (Design for Testability) Engineer. I have Learned different methodologies of DFT such as, Scan Insertion, Scan Compression, Boundary Scan (JTAG) and ATPG Project: 1) JBI design with Scan Chain 3 and Scan Compression ratio with 30x also performed ATPG. 2) Falcon Design with Scan Chain Count 10 and Scan Compression ratio 50x Tools Used: Scan Insertion - DFT Compiler Scan Insertion With Compression - DFT Compiler. ATPG : Tetramax2 Boundary Scan - BSD Compiler ATPG - TetraMax
Stackforce AI infers this person is a DFT Engineer specializing in VLSI design and testing methodologies.
Location: Bengaluru, Karnataka, India
Experience: 7 yrs 4 mos
Skills
- Dft
- Very-large-scale Integration (vlsi)
Career Highlights
- Experienced DFT Engineer with expertise in ATPG and Scan methodologies.
- Successfully completed 4 tapeouts for smart Mobile SoC projects.
- Proficient in using advanced DFT tools like Tetramax2 and DFT Compiler.
Work Experience
MediaTek
DFT Engineer (4 yrs 4 mos)
ChipEdge Technologies Pvt Ltd
Trainee (4 mos)
ST. VINCENT PALLOTTI DEGREE COLLEGE
Assistant Professor (2 yrs 8 mos)
Infosys
Software Trainee (4 mos)
Education
Bachelor's of Engineering at Chhattisgarh Swami Vivekanada Technical University
at Saraswati Shishu Mandir Hr. Sec. School