Sanath Ellaboina

CTO

Hyderabad, Telangana, India14 yrs 3 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

Senior Member of Technical Staff at AMD
Expertise in Physical Design and Timing Analysis
Experience in leading complex semiconductor projects

Stackforce AI infers this person is a Semiconductor Design Engineer with expertise in Physical Design and Timing Analysis.

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Skills

Core Skills

Physical DesignStatic Timing Analysis

Other Skills

Place & RouteSynopsys PrimetimeCadence EncounterTiming ClosureQRCConformal LECFloorplanning

Experience

14 yrs 3 mos

Total Experience

3 yrs 6 mos

Average Tenure

6 yrs 5 mos

Current Experience

Amd

Senior Member of Technical Staff

Nov 2019 – Present · 6 yrs 5 mos · Hyderabad Area, India

Physical DesignStatic Timing AnalysisPlace & RouteSynopsys PrimetimeCadence EncounterTiming Closure+3

Intel corporation

SoC Design Engineer

Jun 2017 – Nov 2019 · 2 yrs 5 mos

Graphene semiconductor services pvt ltd.

Senior Engineer

Aug 2016 – May 2017 · 9 mos · Bengaluru Area, India

Soctronics

Sr. Physical Design Engineer

Nov 2011 – Jul 2016 · 4 yrs 8 mos · Hyderabad Area, India

Education

BITS Pilani Work Integrated Learning Programmes

Master of Technology - MTech — Microelectronics

Dec 2021 – Jan 2024

The Institution of Engineers India

AMIE — Electronics and Communications Engineering

Jan 2013 – Jan 2015

Government Institute Of Electronics

Special Diploma — Embedded Systems

Jan 2008 – Jan 2011

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