Vasanthi Kothamasu

Software Engineer

Andhra Pradesh, India7 yrs 3 mos experience

Highly Stable

Key Highlights

Expert in Physical Design and Low Power Verification.
Proficient in Synopsys tools including ICC2 and Prime Time.
Experienced with 6nm and 7nm technology processes.

Stackforce AI infers this person is a Semiconductor Design Engineer with expertise in Physical Design and Low Power Verification.

Contact

Skills

Core Skills

Physical DesignLow Power Verification

Other Skills

ICC2Prime TimeVC LPShell ScriptingPerlTCLFloorplanningTiming ClosurePlace & RouteTiming

About

Working experience with 6nm & 7nm technologies. Good Knowledge on Synopsys tools ICC2, Prime Time, VC LP. Good knowledge on PNR Flow , ECO Flow, Working experience in Multi Voltage blocks. Expertise in PD FullChip Low Power Verification.

Experience

7 yrs 3 mos

Total Experience

3 yrs 3 mos

Average Tenure

1 yr 4 mos

Current Experience

Amd

Sr. Silicon Design Engineer

Dec 2024 – Present · 1 yr 4 mos

Physical DesignICC2Prime TimeVC LPLow Power Verification

Cerium systems

Sr. Physical Design Engineer

Apr 2022 – Dec 2024 · 2 yrs 8 mos

Physical DesignLow Power Verification

Soctronics

2 roles

Physical Design Engineer

Jan 2019 – Nov 2022 · 3 yrs 10 mos

Physical Design

Physical Design Engineer

Jan 2019 – Apr 2022 · 3 yrs 3 mos

Working experience as Block owner, PD Full chip VC LP owner.

Physical DesignLow Power Verification

Veda iit

Apprentice

Jul 2018 – Jan 2019 · 6 mos · Hyderabad, Telangana, India

Physical Design Engineer Training

Physical Design

Education

R.V.R. & J.C. College of Engineering

Bachelor of Technology — Electronics and Communications Engineering

Jan 2014 – Jan 2018

Narayana Junior College

Intermediate

Jan 2012 – Jan 2014

Sai Aditya School

Jan 2012 – Present

Stackforce found 100+ more professionals with Physical Design & Low Power Verification

Explore similar profiles based on matching skills and experience

Ronil Mandavia

Senior Analyst

at AlphaGrep

Mumbai, India1 yr 9 mos exp

Quantitative Research

Manikanta Gummadidala

Senior Staff Engineer - ASIC Design Verification

at Samsung Electronics

Bengaluru, India11 yrs 4 mos exp

ASIC Design Verification

Akhil Arora

Senior Staff Engineer

at Qualcomm

India17 yrs 9 mos exp

SoC VerificationVerification methodologiesVeloce EmulationSystem Verilog Design and VerificationTechnical Support

Vidhan Singh

Senior Silicon Design Engineer

at AMD

Ayodhya, India5 yrs 8 mos exp

Physical DesignPlace & RouteUnified Power Format (UPF)

Murugan A

Engineering Manager

at MediaTek

Bengaluru, India14 yrs 6 mos exp

VerificationPCIe

Chandra Prakash G.

Principal Software Engineer

at Microsoft

Redmond, United States19 yrs 10 mos exp

EDA toolsbackend servicescloud securitycloud-native microservicescompiler front-end

Amitesh Singh

Sr. ASIC Engineer

at NVIDIA

Bengaluru, India12 yrs 4 mos exp

Multimedia IP VerificationPower Aware VerificationSOC Design VerificationVLSI Design

Durga Dileep Madduri

Senior Engineer

at MediaTek

Bengaluru, India2 yrs 9 mos exp

Static Timing AnalysisSynthesis