Raju Anand — Software Engineer

Good understanding of CMOS Process Flow. Worked on Power Management blocks like Band Gap reference , Low Dropout regulator. Good Understanding of reliability Analysis (Aging, EOS), Monte Carlo Simulation and Post layout Verification. Good working experience on Cadence Tools. Hands on Experienced in full custom layout design of Analog blocks such as Current Mirror,Differential Pair , operational amplifiers of different complex topologies, bias generators, LDO, BGR etc. and complex digital blocks. Strong debug and problem solving skill for DRC, LVS, ERC checks etc. at Top level. Matching Concept(common centroid, interdigitation) Signal Integrity. Good knowledge of layout issues(Latch up, Antenna Effect, IR Drop, Electromigration) Understanding of layout dependent Effects(LDO, STI, WPE, OSE, Density Effect), Duumy Transitor and Dummy Poly. Working Experience in CMOS based 6T SRAM Memory design and Layout, STD CELL design ,layout and characterization. Hands on experience on Digital VLSI Design using XILINX , Synopsys, Mentor Graphics EDA Tools at 180 and 90 nm Technology node. Pre-silicon Validation using ISim on Spartan , Virtex series FPGAs. Hands on experience on Analog VLSI Design Using Synopsys Galaxy Custom designer on 32nm,90nm and Cadence Virtuoso Platform at 180 nm .

Stackforce AI infers this person is a VLSI Design Engineer with expertise in Analog Circuit Design and CMOS technology.

Location: Bengaluru, Karnataka, India

Experience: 11 yrs