Alok Jadhav

Software Engineer

Bengaluru, Karnataka, India11 yrs 5 mos experience

Highly Stable

Key Highlights

Expert in ASIC design and verification methodologies.
Proficient in System Verilog and UVM for complex IPs.
Strong background in low-power design and automation.

Stackforce AI infers this person is a Semiconductor Verification Engineer with expertise in ASIC and digital design.

Contact

Skills

Core Skills

AsicFunctional Verification

Other Skills

System VerilogUVMDigital ElectronicsOVMPERLPower aware VerificationAHB protocolElectronicsProgrammingEngineeringAnalog Circuit DesignImage ProcessingVLSIFPGAField-Programmable Gate Arrays (FPGA)

About

To secure a challenging position where I can effectively contribute my skills as an Engineer, acquiring competent Technical Skills. TECHNICAL AREA OF INTERESTS ASIC design, automation and Verification, Validation, Physical design, FPGA based system design, RTL Design, Physical design, Synthesis/STA, Low-power designs, Digital design. TOOLS KNOWN Cadence RTL compiler, SoC Encounter, ModelSim, Altera Quartus, Cadence NCSim, ICCR, Virtuoso, Synopsys-VCS, Xilinx, ngspice, microwind, Silvaco-TCAD, Psim, Tina-TI. Embedded Pogramming IDE & tools - Keil, MPLAB, MATLAB. LANGUAGES KNOWN Verilog HDL, System Verilog, VHDL, PERL, TCL, C, C++ Basics. Verification Methodologies: OVM, UVM

Experience

11 yrs 5 mos

Total Experience

11 yrs 5 mos

Average Tenure

11 yrs 5 mos

Current Experience

Intel corporation

2 roles

Senior Design Verification Engineer

Aug 2015 – Present · 10 yrs 9 mos · Bengaluru Area, India

Pre-Silicon Logic Verification of Front end design Features in Complex IPs and SoCs.

System VerilogUVMASICDigital ElectronicsFunctional Verification

Intern

Oct 2014 – Jun 2015 · 8 mos · Bangalore

Power aware Verification of State Retention and Non-Retention Registers in low power offload Engine based on checkers and functional coverage using System Verilog and OVM.
Power aware Verification of Isolation Registers in low power offload Engine.
Automation of various aspects in low power offload engine using PERL.
Development of complete verification environment of AHB protocol in OVM.
Behavioral Modelling of Double Synchronizers in System Verilog in order to catch Metastability Issues in verification IP.

System VerilogOVMPERLPower aware VerificationAHB protocolFunctional Verification+1