Om Aditya Paliwal

Software Engineer

Agra, Uttar Pradesh, India4 yrs 9 mos experience
Highly Stable

Key Highlights

  • SoC Design Engineer at Intel India.
  • Strong foundation in VLSI design and RTL design.
  • Experience in front-end development for impactful projects.
Stackforce AI infers this person is a VLSI and Front-end Development specialist with experience in engineering projects.

Contact

LinkedIn

Skills

Core Skills

Soc DesignVerilogFront-end Development

Other Skills

C++cpythonSQLData AnalysisRtableauFinancial AnalysisFinanceEngineering

About

2021 ENI Graduate from BITS Pilani Hyderabad Campus. Interested in the field of vlsi design,verilog and RTL Design

Experience

4 yrs 9 mos
Total Experience
4 yrs 9 mos
Average Tenure
4 yrs 9 mos
Current Experience

Intel corporation

2 roles

SoC Design Engineer

Jul 2021 – Present · 4 yrs 9 mos · Bengaluru, Karnataka, India

SoC DesignVerilog

Graduate Technical Intern

Aug 2020 – Dec 2020 · 4 mos · India

Indian red cross society -ircs (national headquarters, new delhi india)

Summer Intern

May 2019 – Jul 2019 · 2 mos · New Delhi, Delhi, India

  • We worked on revamping the E-Newsletter of IRCSBlood Bank using front end and backend frameworks
Front-end Development

Education

Birla Institute of Technology and Science, Pilani

Bachelor of Engineering - BE — Electrical and Electronics Engineering

Jan 2017 – Jan 2021

Sumeet rahul goel memorial senior sec school

CBSE senior secondary — Science

Jan 2015 – Jan 2017

St pauls church college

10th

Jan 2015 – Present

Stackforce found 100+ more professionals with Soc Design & Verilog

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