Pankaj gupta — Software Engineer
I’m an RTL & FPGA Design Engineer with 5 years of experience in digital design (SystemVerilog/Verilog/VHDL), FPGA programming, and LLM training for silicon workflows. I design and optimize hardware architectures—including protocol analyzers, memory management units, and on-board testing—while driving verification quality with cocotb/QuestaSim. Proficient with Xilinx Vivado, Intel Quartus Prime, and QuestaSim, I focus on timing closure, debugging, and efficiency improvements. Recently, I’ve led dataset and pipeline development to train LLMs on RTL tasks (code generation, bug fixing, testbench creation, and QA). I’m open to opportunities where I can apply this blend of RTL/FPGA engineering and AI-driven tooling to build innovative hardware solutions.
Stackforce AI infers this person is a Digital Hardware Design Engineer with expertise in FPGA and RTL development.
Location: Gurugram, Haryana, India
Experience: 10 yrs 6 mos
Skills
- Fpga Design
- Digital Hardware Design
- Rtl Design
Career Highlights
- 5 years of experience in RTL and FPGA design.
- Expertise in LLM training for silicon workflows.
- Proficient in Xilinx Vivado and Intel Quartus Prime.
Work Experience
Keysight Technologies
Senior FPGA Design Engineer at Keysight Technology (1 yr)
Center for Development of Telematics (C-Do T)
Senior Fpga Design Engineer (1 yr 3 mos)
Qbit Labs
Research And Development Engineer (3 yrs 6 mos)
National Institute of Technology Hamirpur
Student (5 yrs)
Education
Dual degree (M.Tech + B.Tech) at National Institute of Technology Hamirpur-Alumni
