Ritu Gupta

Software Engineer

Bengaluru, Karnataka, India8 yrs 10 mos experience
Most Likely To SwitchHighly Stable

Key Highlights

  • 7+ years in wireless industry engineering.
  • Expert in Physical Design across multiple technology nodes.
  • Proficient in RTL to GDSII flow and verification.
Stackforce AI infers this person is a VLSI design engineer with expertise in physical design and verification in the semiconductor industry.

Contact

Skills

Core Skills

Physical DesignVlsi

Other Skills

Netlist to GDSPlace and RouteSign-offSTAPVMixed Signal InterfaceFloorplanPNRExtractionVerificationC++ProgrammingCadence VirtuosoVerilogMatlab

About

Experienced Engineer with 7+ year of demonstrated history of working in the wireless industry. Skilled in Physical Design and implementation. Worked on various lower lower technology node like 6nm 12nm 28nm 3nm. RTL to GDSII flow including floorplan , place and Route, STA, Physical verification, extraction timing , DRC , LVS , low power design etc.

Experience

8 yrs 10 mos
Total Experience
2 yrs 11 mos
Average Tenure
4 yrs 2 mos
Current Experience

Mediatek

2 roles

Staff Engineer

Promoted

Jun 2025Present · 10 mos · Bengaluru, Karnataka, India

  • Handling Netlist to GDS, Place and Route, Sign-off, STA, PV.
Netlist to GDSPlace and RouteSign-offSTAPVPhysical Design+1

Senior Engineer

Feb 2022Jul 2025 · 3 yrs 5 mos · Bengaluru, Karnataka, India

Hcl technologies

Tech Lead

Dec 2018Feb 2022 · 3 yrs 2 mos · Bangalore

  • Working for Mediatek on 6nm technology node.
  • Worked for client as ST Microelectronics on Physical Design . Handled Mixed signal interface block contain PHY on 7nm Technology Node.
  • Worked for ST Microelectronics on 28nm FDSOI technology. Handled floorplan, PNR, Extraction . Worked on PT and DMSA for block closure.
  • Worked on high frequency Digital block on 14nm technology for PD client @Intel.
Physical DesignMixed Signal InterfaceFloorplanPNRExtractionVLSI

Qualcomm

Engineer

May 2017Nov 2018 · 1 yr 6 mos · Bangalore Area, India

  • Currently working as physical design and verification
Physical DesignVerification

Intel corporation

Intern

Nov 2016Apr 2017 · 5 mos · India

  • Working as intern in Intel Technology India on physical design
Physical Design

Education

Vellore Institute of Technology

Master’s Degree — VLSI Design

Jan 2015Jan 2017

Shri Shankaracharya Technical Campus Bhilai

Bachelor of Engineering (BE) — Electrical and Electronics Engineering

Jan 2011Jan 2014

Govt.Polytechnic, Ambikapur

Diploma — Electronic and Telecommunication

Jan 2008Jan 2011

Holy Cross Hr. Sec. School

High School — Maths and Science

Jan 2007Jan 2008

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