jagadeesh kolisetti — Software Engineer

VLSI Expert – 8+ years of experience in STA, synthesis, and physical design, specializing in high-performance SoC development. Cutting-Edge Tech – Worked on 2nm, 3nm, 4nm, 7nm, and beyond, optimizing designs for advanced semiconductor process nodes. Diverse Applications – Expertise in CPUs, GPUs, modems, mobile SoCs, IoT, and automotive chipsets, delivering high-speed, low-power solutions. STA & Timing Closure – Extensive experience in multimode, multi-corner STA, constraint validation, and timing signoff across 220+ corners. Clock & Signal Integrity – Strong background in CTS, skew balancing, crosstalk noise analysis, and derating methodologies for robust design closure. EDA & Automation – Proficient in PrimeTime, Tempus, ICC2, Tweaker, and TCL scripting for automated timing analysis and optimization. Full-Chip Integration – Led STA for large-scale SoCs, integrating multiple blocks with complex clock architectures and achieving timing convergence. Optimization & ECOs – Skilled in advanced ECO strategies, including net fixes, cell resizing, buffer insertion, and hold/setup path optimizations. Advanced STA Techniques – Hands-on experience in OCV/AOCV analysis, DMSA-based timing closure, and debugging critical timing bottlenecks. Signoff & Quality Checks – Executed detailed timing sanity checks, SDC validation, and pre/post-CTS analysis to ensure first-pass silicon success.

Stackforce AI infers this person is a VLSI design engineer specializing in high-performance semiconductor solutions.

Location: Bengaluru, Karnataka, India

Experience: 6 yrs 11 mos