Anand P S

Software Engineer

Bengaluru, Karnataka, India6 yrs 10 mos experience

Most Likely To SwitchAI Enabled

Key Highlights

5 years of experience in VLSI and RTL design.
Expertise in developing complex IPs and CDC solutions.
Hands-on experience with leading EDA tools.

Stackforce AI infers this person is a VLSI Design Engineer with a strong focus on RTL development and CDC solutions.

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Skills

Core Skills

Digital ElectronicsRtl DesignIot

Other Skills

DFTSystemVerilogCDCLINTPCB DesigningMachine LearningArtificial Intelligence (AI)Python (Programming Language)Pandas (Software)VerilogSystem on a Chip (SoC)Field-Programmable Gate Arrays (FPGA)RTL CodingXilinx VivadoManagement

About

Progressing and Passionate Design Engineer with Flips and Flops in life. Having 5 years of experience in VLSI (RTL Designing, ASIC, Linting, CDC, FPGA, and STA). Extensive hands-on experience in various EDA tools such as Vivado, Quartus, Spyglass, Cadence HAL, Cadence NCSIM (Simvision), Mentor HDS, Mentor Model Sim. Also having from scratch experience in the Physical Adapter layer design of MIPI Unipro 1.8. Currently working at UST, Bengaluru as Engineering Designer, Developing Frontend RTL for complex IPs. Currently developing Physical Adapter Layer (L1.5 layer) of MIPI UniPro 1.8. with Modular level and top-level linting using Cadence HAL and Solving CDC issues in the block level. Previously worked at Wipro Limited Hyderabad, Mainly works on RTL coding, Static Timing Analysis (STA), CDC solutions, and Spyglass CDC and LINT.

Experience

6 yrs 10 mos

Total Experience

2 yrs 3 mos

Average Tenure

4 yrs

Current Experience

Amd

2 roles

Sr. Silicon Design Engineer

Jun 2024 – Present · 1 yr 11 mos

Silicon Design Engineer 2

May 2022 – Jun 2024 · 2 yrs 1 mo

DFTDigital Electronics

Ust

2 roles

Senior RTL Engineer

Promoted

May 2021 – Jun 2022 · 1 yr 1 mo

Currently at Sevitech Systems PVT LTD (UST Global Company) / Working as a contract employee for Qualcomm, Iam responsible for SoC level Connectivity, SoC Level IRQ Connectivity flow and CDC static checks(PLDRC Lint , CDC etc.).
SoC Integration Team
Responsibities
>CDC Static Checks (SoC)
>PLDRC Static Checks(SoC)
> SoC IRQ Connectivity Flow
>Uflow (pldrc,cdc,synth, dft etc.)
>Chip Core Connectivity and Cleanup

RTL DesignSystemVerilog

Associate Engineering Designer

Jul 2020 – Apr 2021 · 9 mos

I am Responsible for designing front-end RTL for MIPI Unipro 1.8 physical adapter layer (L1.5) and other complex IPs. Along with the development, the major CDC and LINT checks are performed and suitable CDC Synchronizers are developed and reused.

Wipro limited

VLSI Engineer

Jun 2019 – Jul 2020 · 1 yr 1 mo · Greater Hyderabad Area

I am Responsible for designing front-end RTL for various design specs for the customer. Along with the development, the major CDC and LINT checks are performed and suitable CDC Synchronizers are instantiated, Major STA and Constraint development tasks are performed. Also, responsible for the automation of tools and other tasks using scripting.

Neo green labs

Hardware Intern

Mar 2019 – Jun 2019 · 3 mos · Kochi, Kerala, India

I am responsible for handling various sessions of IoT, Home Automation, PCB Designing using ORCAD, etc at various colleges, institutes, and various technical events. Also responsible for handling small projects based on IoT. Developed IoT hardware on an automated attendance management system using a fingerprint sensor using ESP8266 along with mobile and web applications.