Vikram Kuralla

Director of Engineering

Hyderabad, Telangana, India23 yrs 7 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

23 years of experience in VLSI product life-cycle.
Led teams of over 80 engineers in ASIC and SOC design.
Expert in AI/ML methodologies for VLSI design flows.

Stackforce AI infers this person is a VLSI and ASIC design expert with extensive experience in semiconductor technology.

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Skills

Core Skills

Soc DesignHardware ArchitectureAsicSoc ManagementDftLogic Synthesis

Other Skills

Account ManagementLogic DesignLow-power DesignATPGFloorplanningPlace & RouteTiming ClosureStatic Timing AnalysisVLSIARMSemiconductorsVerilogPerlVHDLEDA

About

High performing professional with 23 years of experience in the field of VLSI covering the complete product life-cycle, right from Architecture to Silicon. * Experience in the areas of SOC Integration, Synthesis, STA, DFT, Physical Design and Post Silicon activities. * Execution of Turnkey ASIC & SOC Designs in different domains like Client Compute, Artificial Intelligence, Base band Radio, and Networking chips on leading edge process nodes. * Experience with Test Chip Designs for Foundation IP ( standard cells, memory, IO, Analog), right from architecture till IP qualification on Silicon. * Experience with development as well deployment of EDA flows and Methodologies focusing on improving PPA and Quality. * Strong experience in Building and managing teams. * Mentoring & Coaching

Experience

23 yrs 7 mos

Total Experience

3 yrs 4 mos

Average Tenure

4 yrs 9 mos

Current Experience

Amd

Director - Silicon Design

Jul 2021 – Present · 4 yrs 9 mos · Hyderabad, Telangana, India · On-site

Leading SoC's & Chiplets on latest technology nodes
Development and Adoption of AI/ML Methodologies in VLSI Design Flows, targeting Productivity Improvements and Cost Savings

SoC DesignHardware ArchitectureSOC ManagementASICDFT

Invecas

2 roles

Director - SOC Design

Promoted

Apr 2018 – Jul 2021 · 3 yrs 3 mos

Responsible for Turnkey ASIC & SOC Designs in different domains like Artificial Intelligence, Base band Radio, Networking, Quantum Compute on leading edge process nodes.
SPOC for multiple Tier1 customers, engaging right from SOW, Costing and delivery of project and making sure meeting all milestones and quality
Built and lead a strong team of 80+ Engineers (Owning all Front End and DFT Functions)
Lead Test Chip Designs starting from Architecture till Silicon Qualification of several IP's (For Logic, Memory, IO, Analog IP)
Owning and driving the methodology on all Front End Design activities in SoC Design, DFT focusing on Quality and PPA
ISO Process Owner for ASIC Design Process
Resource Planning
Customer Engagement
Modeling of Foundation IP's
ATE Bringup and Production Support

ASICHardware ArchitectureSOC ManagementAccount ManagementDFT

Senior Manager - Design Engineering

Oct 2014 – Apr 2018 · 3 yrs 6 mos

Amd

Senior Staff Engineer (SMTS)

Jan 2010 – Oct 2014 · 4 yrs 9 mos · Hyderabad Area, India · On-site

SoC Implementation lead for Client Fusion APU SoC Programs (Kabini, Carrizo)
Leading complex Client APU SoC programs integrating 120+ hierarchical blocks
Co-ordination between different teams spread across the geography
Bridging the gap between IP and SoC teams by establishing common standards and procedures
Key methodology lead driving for common methodologies across different Business Units in the areas of SoC Integration and Implementation
Technical Reviewer for AATC (AMD internal technical conference)

ASICLogic DesignLogic SynthesisLow-power DesignSOC ManagementSoC Design

Arm embedded technologies pvt ltd

Staff Engineer & Skill Group Lead

Aug 2008 – Jan 2010 · 1 yr 5 mos · Bangalore · On-site

Implementation of CPU (Cortex Series) and Graphics Core (Mali Series) Designs
Developing Reference Methodology, Bench-marking and PPA for Mali Graphics core designs on different technology nodes (RTL2GDSII)
SoC DFT for ASIC Platform that includes Mali and Cortex processors
Presented Technical Paper in Synopsys Tech Forum (SNUG) on "Implementation of ARM Mali Graphics processor using MIM and ILM of SNPS Galaxy Platform"

ATPGDFTFloorplanningLogic SynthesisLow-power DesignPlace & Route+1

Gdmicro (currently soctronics)

Staff Engineer - SoC Design

Jul 2006 – Aug 2008 · 2 yrs 1 mo · Hyderabad Area, India · On-site

Chip Lead for SoC Projects in Machine2Machine (M2M) Technology
Developed couple of Hardware Accelerators
SoC Integration, Clocking, DFT, Synthesis and STA

Veda iit

Design Engineer

Nov 2003 – Jul 2006 · 2 yrs 8 mos · Hyderabad, Telangana, India

Developing Digital Controllers and Hardware Accelerators
Handling FPGA to ASIC Conversion Projects
Groomed 350+ fresh engineering graduates in Logic Design, DFT, Synthesis and STA