Nishant Giri

Engineering Manager

Andhra Pradesh, India15 yrs 2 mos experience
Highly Stable

Key Highlights

  • 12 years of experience in semiconductors industry
  • Expert in Power Verification and Validation
  • Strong leadership in managing engineering teams
Stackforce AI infers this person is a semiconductor engineering expert with strong capabilities in power validation and verification.

Contact

LinkedIn

Skills

Core Skills

Power VerificationFpgaPower ValidationFlow Automation

Other Skills

ACAPCustomer design analysisDefect request analysisCustomer CR analysisSimulation based equivalence checkHW Power ValidationSimulation DebuggingFPGA block power validationPower Optimization feature verificationAutomationFlow automation developmentSystem VerilogVHDL testcase developmentSynthesis ValidationPerl Script

About

Engineering Manager with 12 Years experience with a demonstrated history of working in the semiconductors industry. Skilled in Power Verification, Simulation, Verilog, VHDL, Perl, TCL, Shell Scripting and EDA. Strong engineering professional with a Master of Technology (M.Tech.) focused in Microelectronisc & VLSI from West Bengal University of Technology.

Experience

15 yrs 2 mos
Total Experience
5 yrs 8 mos
Average Tenure
3 yrs 10 mos
Current Experience

Amd

Engineering Manager

Jul 2022 – Present · 3 yrs 10 mos · Hyderabad, Telangana, India

  • Managing power validation team FPGA/ACAP
  • Customer design analysis
Power VerificationFPGAACAPCustomer design analysis

Xilinx

4 roles

Section Manager SW Development

Oct 2021 – Jun 2022 · 8 mos

  • Managing and leading Power validation for Xilinx devices
  • Incoming defect request analysis against application
Power validationDefect request analysisPower Validation

Senior Design Engineer II

Jun 2020 – Sep 2021 · 1 yr 3 mos

  • Leading Power validation team
  • Customer CR analysis
  • Simulation based equivalence check for Power Optimization features
Power validationCustomer CR analysisSimulation based equivalence checkPower Validation

Senior Design Engineer

Promoted

Jun 2017 – Jun 2020 · 3 yrs

  • Leading Power Verification
  • HW Power Validation, Simulation Debugging,
Power VerificationHW Power ValidationSimulation Debugging

Software Engineer

Nov 2013 – May 2017 · 3 yrs 6 mos

  • Power Verification
  • FPGA block power validation, Power Optimization feature verification, Automation
Power VerificationFPGA block power validationPower Optimization feature verificationAutomation

Interra systems india pvt. ltd.

Senior Engineer

Nov 2010 – Oct 2013 · 2 yrs 11 mos · Bangalore

  • Development of flow automation used in Intel Mobile Communication. System Verilog, VHDL testcase development, Synthesis Validation.
Flow automation developmentSystem VerilogVHDL testcase developmentSynthesis ValidationFlow Automation

Education

West Bengal University of Technology, Kolkata

Master of Technology (M.Tech.) — Microelectronisc & VLSI

Jan 2008 – Jan 2010

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