Aug 2017 – Mar 2020 · 2 yrs 7 mos · Bangalore, India

• Automotive/ChipCardSecurity/IndustrialPowerControl/PowerManagement&Multimarket SoC TestChips end-to-end qualification
• Responsible for State of the art Design Flow infrastructure Development

Jan 2012 – Jul 2017 · 5 yrs 6 mos · Bangalore

• Mainframe Enterprise Server Processor (System Z) - RTL Logic Design and Functional Verification :
• + Project management of India owned units/sub-block/core/un-core design/verification deliverables
• + Responsible for processes setup, driving project schedules, tracking key milestones, conduct reviews, drive learnings, improve efficiency/innovation, manage risks and develop mitigation plans
• + Lead group of ~35 people to develop and execute test plans and meet verification goals
• + Collaborate with other units/chip owners globally, physical design teams on timing/power takedown, post-Si teams to close bugs, EDA team for any tools/methodology improvements
• + Contributed to the success of three generations of tape-outs
• EDA :
• + Owning development of IBM internal CAD tools/methodology in the areas of formal (both model and equivalence checking), cycle based simulation, debugging, regression framework, aspect oriented, and infrastructure
• + Interfacing with large design teams across the globe from System P, Z processors and ASICs to deploy/define next generation features/methodology, support user issues and help them taping out their projects on time
• + Driving yearly plans/strategy

Mar 2011 – Jan 2012 · 10 mos

• - Manage Emulaiton/TBX/Post-si team to deliver testplans and debug for Graphics chips

Mar 2008 – Mar 2011 · 3 yrs

• + Functionally leading Unit/Cluster/Fulchip verification of integrated GPU chips (five generations spanning in 4 yrs). Chips support DX9/10/11; OpenGL, OpenCL.
• + Good understanding of functional verification domain - like verification strategies, directed/constrained random and stress test generation, verification infrastructures(OVM) and verification and/or debug flows. Formal verification(property and equivalence), simulation, emulation. Both RTL and GLS.
• + Manage and lead a team of design and verification engineers to successfully execute projects and tasks on time with quality
• + Good hands on experience to gauge technical complexity and guide less experienced engineers within the team
• + Conversant with front end flows and tools/methodologies to improve efficiency for VLSI logic design and/or functional verification
• + Meet functional/timing/stress/performance validation goals
• + Interact with micro-architects/designers/SW modeling/Emulation/post-si teams during testplan reviews
• + Good arch overview of 3D/Media/Blitter/Image Enhancement design/validation flows
• + Involve in driving testplans for new features, validate, introduce new verification methodologies to catch more corner bugs
• + Program management (verification) of three parallel projects with several SKUs. Involves lot of multiplexing.
• + Experience of leading ~25 people engineering team with technical breadth of Architecture/uArch/Design/Functional Verification/DFT/Fault Grading/Emulation
• + People management (10 direct reports)
• + Co-ordinate with heavy multi-site stakeholders on the progress and reporting risks
• + Actively participate in driving innovations within group. Contributed to 11 technical papers 8 posters so far
• + Lead the 'boot-camp/training' to new employees on graphics design and verification
• + Had undergone several quality technical/managerial trainings

Feb 2006 – Mar 2008 · 2 yrs 1 mo

• + Responsibile for functional verificaiton tool flows and methodology deployment and support
• + Interface between design teams and EDA
• + Driver new methodologies (formal, assertions, coverage, CDC, debug, testbench automation, etc.,)

Jan 2003 – Jan 2006 · 3 yrs

• Responsible for unit/SoC level pre-Si verification
• Develop and support latest verification methodologies and flows to Wireline/Wireless/Automotive/Security SoC chips

Jan 2000 – Jan 2003 · 3 yrs

• Mobile SoC level pre-Si verification of I2C,GPIO,Timer units and interfaces
• Develop and support latest verification methodologies and flows to wireless/wireless/automobile/security SoC chips

Jan 1999 – Jan 2000 · 1 yr

• Responsible for DFT Tools and Flows Qualification - MBIST, LBIST, Scan