Partha Sarathi Gujjari

Engineering Manager

Hyderabad, Telangana, India17 yrs 3 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

Experienced in VLSI and ASIC design.
Strong background in clock distribution and physical design.
Proven leadership as Engineering Manager at Intel.

Stackforce AI infers this person is a VLSI and ASIC design expert with extensive experience in semiconductor engineering.

Contact

Skills

Core Skills

Clock DistributionVlsi

Other Skills

Physical DesignDRCTiming ClosureASICTimingFloorplanningPrimetimeStatic Timing AnalysisClock Tree SynthesisTCLPhysical VerificationLVSCadence VirtuosoRouteScripting

Experience

17 yrs 3 mos

Total Experience

2 yrs 2 mos

Average Tenure

9 yrs 7 mos

Current Experience

Intel corporation

3 roles

Engineering Manager (Clocking)

Promoted

Mar 2023 – Present · 3 yrs 1 mo

Clock DistributionVLSI

Clocking Design Engineer

Apr 2020 – Present · 6 yrs

Clock DistributionVLSI

SD Engineer

Sep 2016 – Apr 2020 · 3 yrs 7 mos

Clock DistributionVLSI

Soft machines

Sr Design Engineer I

Jun 2016 – Sep 2016 · 3 mos · Hyderabad Area, India

Clock DistributionVLSI

Imagination technologies

Hardware Design Engineer

Aug 2013 – May 2016 · 2 yrs 9 mos · Hyderabad Area, India

Clock DistributionVLSI

Posedge

Sr. Engineer (PD)

Feb 2013 – Jul 2013 · 5 mos · Hyderabad Area, India

Clock DistributionVLSI

Texas instruments

Contractor

Jun 2012 – Dec 2012 · 6 mos · Bengaluru Area, India

Clock DistributionVLSI

Synapse techno design innovations pvt ltd

Sr. PD Engineer

May 2012 – Jan 2013 · 8 mos · Bengaluru Area, India

Experience on 28nm tech node designs.

Clock DistributionVLSI

Vedaiit

Sr. Engineer (Physical Design)

Jan 2012 – May 2012 · 4 mos · Hyderabad

Experience on 45nm, 65nm, 90nm, etc.designs.
Worked on P and R Projects at SoCtronics, Hyderabad.
Timing Closing of Timing, Congestion and Power critical blocks/tiles.
DRC/LVS.
Tools: SoC Encounter, PT-Si, Caliber, StarRC, Conformal, Ostrich, etc.

Clock DistributionVLSI

Veda iit

ASIC Design Engineer (PD)

Sep 2008 – Dec 2011 · 3 yrs 3 mos · Hyderabad Area, India

Education

Jawaharlal Nehru Technological University, Hyderabad

Master of Technology (M.Tech.) — VLSI System Design

University of Califonia, SC

Certification in VLSI Physical Design — VLSI Physical Design

Jan 2007 – Jan 2007

Institute of Electronics and Telecommunications Engineering

BTech — Electronics nd Telecommunications

Jan 2000 – Jan 2005

QQ Govt. Polytechnic, Hyderabad

Diploma in Electronics and Communications — ECE

Jan 1994 – Jan 1996

Govt. High School, VNC, Hyderabad

SSC

Jan 1985 – Jan 1989

Stackforce found 100+ more professionals with Clock Distribution & Vlsi

Explore similar profiles based on matching skills and experience

Ritika ..

Staff Engineer

at Qualcomm

Delhi, India15 yrs 5 mos exp

Physical DesignTiming Closure

NITISH KUMAR

Senior Staff Engineer

at Samsung Semiconductor

Bengaluru, India7 yrs 9 mos exp

Physical DesignStatic Timing Analysis

Vivek Shrivastva

Staff Engineer

at Qualcomm

Noida, India10 yrs 5 mos exp

Physical DesignClock Tree SynthesisComputer Architecture

Sneha Tutika

SoC Staff Engineer

at Synopsys Inc

Hyderabad, India10 yrs 11 mos exp

Physical DesignVLSI

Animesh Sharma

Silicon Design Engineer

at AMD

Bengaluru, India14 yrs 9 mos exp

Static Timing Analysis3DIC Design

Prajjwal Rana

Analog Design Engineer

at Texas Instruments

Bengaluru, India0 mo exp

Analog DesignHigh-speed Digital DesignRF Design

Navin Kanodia

Creative Director & Principal Interior Stylist

at S. T. Unicom Pvt. Ltd.

Mumbai, India31 yrs 3 mos exp

Brand DevelopmentClient EngagementCreative DirectionCustomer EngagementDesign Management

Aman Dayal

Lead Software Engineer

at Cadence

Bengaluru, India6 yrs 2 mos exp

Static Timing AnalysisSynopsys PrimetimeDevOpsAutomationSoftware Quality Assurance