V

Vivek Shrivastva

Software Engineer

Noida, Uttar Pradesh, India10 yrs 5 mos experience
Most Likely To SwitchHighly Stable

Key Highlights

  • Over 10 years of experience in Physical Design.
  • Expertise in RTL to GDSII project handling.
  • Strong background in low power designs and timing closure.
Stackforce AI infers this person is a Semiconductor Design Engineer with expertise in Physical Design and Implementation.

Contact

Skills

Core Skills

Physical DesignClock Tree SynthesisComputer Architecture

Other Skills

Power ManagementScriptingClockingDevice PhysicsCommunicationAlgorithmsElectrical EngineeringPython (Programming Language)Clock DistributionRTL DesignSystemVerilogSynopsis ICCAgilent ADSMatlabC

About

~10+ years of hands on experience in Physical Design and Implementation. RTL2GDSII project handling, Low power designs, Logical and Physical Synthesis, Floor-planning, PnR , CTS, Timing CLosure, Timing and PV sign-off, process automation and tool development, Standalone IPs/CORE and block level PnR handling. + Masters in Electrical Engineering from IIT Kanpur, (2015 passout) + Tools Experience --> PnR - Synopsys ICC/ICC2/FC/Innovus(Primary), Cadence Innovus (Secondary) Synthesis - Synopsys Design Compiler Timing Closure - Prime Time, Tweaker -F1 (Dorado) Microwave Designs Related - Agilant Advance Design System (ADS), CST, Ansoft HFSS + Programming Language/Scripting --> Scripting Language - Tcl/Tk Programming Language - C, MATLAB,Python + Shell Scripting --> C-shell and BASH + Platforms --> Linux, Microsoft Windows + Technical Strength - Logical and Physical synthesis , Floor-planning, CTS, PnR, STA, Chip finishing and verification, automation & tool design,PnR Convergence, Clocking, Project Execution management. + Personal Strength - Team Player, Good analysis and debug, Flexible Working, + Hobbies --> Singing, Cooking

Experience

10 yrs 5 mos
Total Experience
3 yrs 5 mos
Average Tenure
5 yrs 5 mos
Current Experience

Qualcomm

3 roles

Staff Engineer

Dec 2024Present · 1 yr 4 mos

Senior Lead Engineer

Apr 2023Dec 2024 · 1 yr 8 mos

Senior Lead Engineer

Oct 2020Mar 2023 · 2 yrs 5 mos

Clock Tree SynthesisPower ManagementPhysical Design

Samsung electronics

3 roles

Staff Engineer

Apr 2019Oct 2020 · 1 yr 6 mos

Computer ArchitecturePhysical Design

Associate Staff Engineer

Apr 2018Mar 2019 · 11 mos

Physical DesignScripting

Lead Engineer

Jun 2017Mar 2018 · 9 mos

ClockingPhysical Design

Mediatek

Design Engineer

Jul 2015May 2017 · 1 yr 10 mos · Greater Bengaluru Area

  • Block level design implementation from netlist to GDS including timing closure and PV closure.
  • Libraries management and control.
  • GUI based Sign-off automation tool development and owner.
  • Working with cross site team members on various design related issues.
Device PhysicsPhysical Design

Education

Indian Institute of Technology, Kanpur

Master of Technology (M.Tech.) — Electrical Engineering

Jan 2013Jan 2015

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