Vivek Shrivastva — Software Engineer
~10+ years of hands on experience in Physical Design and Implementation. RTL2GDSII project handling, Low power designs, Logical and Physical Synthesis, Floor-planning, PnR , CTS, Timing CLosure, Timing and PV sign-off, process automation and tool development, Standalone IPs/CORE and block level PnR handling. + Masters in Electrical Engineering from IIT Kanpur, (2015 passout) + Tools Experience --> PnR - Synopsys ICC/ICC2/FC/Innovus(Primary), Cadence Innovus (Secondary) Synthesis - Synopsys Design Compiler Timing Closure - Prime Time, Tweaker -F1 (Dorado) Microwave Designs Related - Agilant Advance Design System (ADS), CST, Ansoft HFSS + Programming Language/Scripting --> Scripting Language - Tcl/Tk Programming Language - C, MATLAB,Python + Shell Scripting --> C-shell and BASH + Platforms --> Linux, Microsoft Windows + Technical Strength - Logical and Physical synthesis , Floor-planning, CTS, PnR, STA, Chip finishing and verification, automation & tool design,PnR Convergence, Clocking, Project Execution management. + Personal Strength - Team Player, Good analysis and debug, Flexible Working, + Hobbies --> Singing, Cooking
Stackforce AI infers this person is a Semiconductor Design Engineer with expertise in Physical Design and Implementation.
Location: Noida, Uttar Pradesh, India
Experience: 10 yrs 5 mos
Skills
- Physical Design
- Clock Tree Synthesis
- Computer Architecture
Career Highlights
- Over 10 years of experience in Physical Design.
- Expertise in RTL to GDSII project handling.
- Strong background in low power designs and timing closure.
Work Experience
Qualcomm
Staff Engineer (1 yr 4 mos)
Senior Lead Engineer (1 yr 8 mos)
Senior Lead Engineer (2 yrs 5 mos)
Samsung Electronics
Staff Engineer (1 yr 6 mos)
Associate Staff Engineer (11 mos)
Lead Engineer (9 mos)
MediaTek
Design Engineer (1 yr 10 mos)
Education
Master of Technology (M.Tech.) at Indian Institute of Technology, Kanpur