Rochak vaid

Software Engineer

Bengaluru, Karnataka, India12 yrs 7 mos experience
Most Likely To SwitchHighly Stable

Key Highlights

  • Over 10 years of experience in semiconductor design.
  • Expertise in RTL to GDS flow and timing signoff.
  • Proven track record in high-speed server designs.
Stackforce AI infers this person is a Semiconductor Design Expert with a focus on Physical Design and Timing Analysis.

Contact

Skills

Core Skills

Physical DesignStatic Timing Analysis

Other Skills

RTL to GDS flowP&R using ICC2power signoff flowhigh speed server designsSynthesis using Genus/DC-TOPOP&R (innv/icc)PNRsynthesisTiming ClosurePerl Automationautomation flowTCLLayout Versus Schematic (LVS)Design Rule Checking (DRC)

About

As a Senior Staff Engineer at MediaTek, I leverage my extensive experience in physical design and timing signoff to deliver high-quality solutions for complex semiconductor designs. With over 10 years of experience in the field, I have developed a strong expertise in RTL to GDS flow, power signoff, and high-speed server designs.

Experience

12 yrs 7 mos
Total Experience
3 yrs 1 mo
Average Tenure
4 yrs 3 mos
Current Experience

Mediatek

Senior Staff Engineer

Feb 2022Present · 4 yrs 3 mos · Bengaluru, Karnataka, India

Physical DesignStatic Timing Analysis

Hcl technologies ltd

Senior Technical Lead

Jul 2017Feb 2022 · 4 yrs 7 mos

  • Worked on RTL to GDS flow in Timing and congestion critical blocks, P&R using ICC2 and cleanup of all other side flows using different sign off tools
  • Developed power signoff flow (Redhawk)
  • Handle high speed server designs with operating frequency of 2.4GHz
RTL to GDS flowP&R using ICC2power signoff flowhigh speed server designsPhysical DesignStatic Timing Analysis

Capgemini engineering

Senior Consultant

Jun 2016Jul 2017 · 1 yr 1 mo

  • Physical design
Physical DesignStatic Timing Analysis

Stmicroelectronics

Engineer

Oct 2013Jun 2016 · 2 yrs 8 mos

  • Worked on RTL to GDS flow in Timing and congestion in blocks, Synthesis using Genus/DC-TOPO, P&R (innv/icc) & Methodology flow developer
RTL to GDS flowSynthesis using Genus/DC-TOPOP&R (innv/icc)Physical Design

Atrenta

Tr. Software Engineer

Mar 2013Oct 2013 · 7 mos

  • Worked in EDA industry (Synopsys) .

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