Prasanjit Bengani

Software Engineer

Bengaluru, Karnataka, India14 yrs 2 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

Expert in CPU design verification with extensive experience.
Proficient in System Verilog and UVM methodologies.
Contributed to multiple CPU projects at NVIDIA.

Stackforce AI infers this person is a Semiconductor Design Engineer with expertise in CPU verification and design methodologies.

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Skills

Core Skills

Cpu Design VerificationSystem VerilogFunctional Verification

Other Skills

UVMCPU VerificationTestplansSimulationWaveform viewersCache coherencyTestbench developmentCComputer ArchitectureProgrammingMicrocontrollersElectronicsASICMachine LearningVery-Large-Scale Integration (VLSI)

About

Learn, Enjoy and Grow. I have the potential to develop my skills from experience and can handle my responsibilities quite well. I am currently working on the design verification of the CPU (part of the Tegra- chip). I've contributed to 5 CPU projects.

Experience

14 yrs 2 mos

Total Experience

4 yrs 11 mos

Average Tenure

11 yrs 4 mos

Current Experience

Nvidia

2 roles

ASIC Engineer (CPU Design Verification)

May 2015 – Present · 10 yrs 11 mos · Bengaluru Area, India

CPU Verification:
I am responsible for writing comprehensive testplans to dictate the verification strategy for unit and integration TB.
I work on System Verilog UVM testbench and write sequences to stimulate/verify the design. I develop scoreboards and checkers, and triage simulation failures using waveform viewers like Verdi and other means. I write coverage and create directed and random tests to hit interesting corner cases to close out the design verification process.
I review Architectural and micro-architectural documents/specs and provide feedback.
Currently, I am working in the Cache coherency team responsible for maintaining memory consistency, ordering, and coherence across the cache hierarchy.
Involved in the verification of the Load, Store, and Data Cache Unit using System Verilog (UVM).
Involved in the verification of the unit in NOC(Network On Chip) that bridges two different units talking in two different protocols.

System VerilogUVMCPU VerificationTestplansSimulationWaveform viewers+2

Intern

Jul 2014 – Dec 2014 · 5 mos · Bangalore

Worked on the functional verification of Denver CPU (part of the Tegra- chip). Used System Verilog (UVM) for creating testbench infrastructure.

System VerilogUVMFunctional Verification

Concordia university

Intern

Jun 2014 – Jul 2014 · 1 mo

Program of MITACS GLOBALINK 2014.
Selected from a talent pool spanning 7 countries (India, China, Brazil, Mexico, Saudi Arabia, Turkey, Vietnam) for a scholarship to pursue a research internship in Canada