Sudheer Medudula — Software Engineer

Verification Engineer with extensive experience in verifying complex systems, including CPU and 5G MODEM at IP and subsystem levels. Skilled in developing scalable and reusable testbenches for RTL verification using System Verilog, UVM, and assembly languages. Delivering high-quality verification solutions with a proven track record of success Technical Skills: • Hardware Verification language: System Verilog, Assembly language. • Methodology: UVM • Tools Used: Synopsys VCS, Synopsys Verdi, Mentor Questasim. • Technologies worked on: CPU, MODEM, AMBA-AXI

Stackforce AI infers this person is a Hardware Verification Engineer with expertise in complex system verification.

Location: Bengaluru, Karnataka, India

Experience: 8 yrs 8 mos