raghu venegalla

CTO

Karnataka, India14 yrs 9 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

Senior Lead Engineer with extensive ASIC design experience.
Expert in Physical Design and Static Timing Analysis.
Proficient in multiple EDA tools and methodologies.

Stackforce AI infers this person is a VLSI design expert specializing in ASIC development.

Contact

Skills

Core Skills

Physical DesignStatic Timing Analysis

Other Skills

P&RSTASynthesisASICVLSIVerilogTiming ClosureSoCTCLEDADRCPlace & RouteRTL codingModelSimLVS

Experience

14 yrs 9 mos

Total Experience

7 yrs 4 mos

Average Tenure

11 yrs 1 mo

Current Experience

Qualcomm

Senior Lead Engineer

Mar 2015 – Present · 11 yrs 1 mo · Bengaluru Area, India

P&RSTASynthesisPhysical DesignStatic Timing AnalysisASIC+23

Sicon design technologies pvt. ltd.

Design Engineer

Jun 2011 – Feb 2015 · 3 yrs 8 mos · Bengaluru Area, India

Education

Vignan University

MTech(VLSI)

Stackforce found 100+ more professionals with Physical Design & Static Timing Analysis

Explore similar profiles based on matching skills and experience

Avilash Mohanty

Senior Physical Design Engineer

at NVIDIA

Delhi, India8 yrs 9 mos exp

Raja Mondal

Lead Engineer

at Cadence

Bangalore Urban, India8 yrs 2 mos exp

Shubhankar Das

Lead Engineer

at Qualcomm

Faridabad, India10 yrs 1 mo exp

Nikhil Singh

Silicon Design Engineer 2

at AMD

Itarsi, India3 yrs 8 mos exp

SystemVerilogUniversal Verification Methodology (UVM)

Manuj Verma

Senior Software Engineering Manager

at Cadence Design Systems

India24 yrs 9 mos exp

Swetha Gunda

Senior Technical Manager

at AMD

Bengaluru, India18 yrs 6 mos exp

Himanshu Gupta

Digital Design Engineer

at Intel Corporation

Lucknow, India1 yr 9 mos exp

Digital Circuit DesignVLSI

Dimple Lalwani

ASIC Design Engineer

at Meta

Bengaluru, India18 yrs 5 mos exp

SoCASIC