Uzzal Bhaumik

CTO

Delhi, India25 yrs 5 mos experience

Highly Stable

Key Highlights

Expert in Static Timing Analysis and Physical Design.
Proven leadership in technical roles across major companies.
Strong background in ASIC and VLSI methodologies.

Stackforce AI infers this person is a VLSI Design Expert with extensive experience in ASIC development.

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Skills

Core Skills

Static Timing AnalysisPhysical Design

Other Skills

physical optimizationclock tree synthesisnoise optimizationglitch optimizationLogic Synthesisvhdl analyzerverilog analyzerTimingEDAAlgorithmsMagmaASICVLSIDebuggingSoC

Experience

25 yrs 5 mos

Total Experience

3 yrs 4 mos

Average Tenure

3 yrs 4 mos

Current Experience

Amd

Principal Member of Technical Staff

Jan 2023 – Present · 3 yrs 4 mos · Hyderabad, Telangana, India · Remote

Static Timing Analysisphysical optimizationclock tree synthesisnoise optimizationglitch optimizationLogic Synthesis+22

Synopsys inc

Senior Staff Engineer

Oct 2012 – Jan 2023 · 10 yrs 3 mos · New Delhi Area, India

Ansys, inc.

Software Architect

Apr 2012 – Nov 2012 · 7 mos

Magma design automation

2 roles

Architect

Promoted

Aug 2008 – Mar 2012 · 3 yrs 7 mos

SMCS

Jul 2007 – Aug 2008 · 1 yr 1 mo

Cadence design systems

MCS

Jan 2006 – Jun 2007 · 1 yr 5 mos

Cadence design systems india pvt ltd

MCS

Jan 2006 – Jan 2007 · 1 yr

Sequence

project leader

Oct 2004 – Dec 2006 · 2 yrs 2 mos

Interra systems india pvt ltd

Project Leader

Jan 1999 – Jan 2003 · 4 yrs

Interra systems

Lead Engg

Jan 1999 – Jan 2003 · 4 yrs

Delsoft

software engg

Jan 1999 – Jan 2001 · 2 yrs

Education

Jadavpur University

BE — comp. sc.

Jan 1995 – Jan 1999

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