S

Sareena P M

Software Engineer

Bengaluru, Karnataka, India9 yrs 5 mos experience
Most Likely To SwitchHighly Stable

Key Highlights

  • Experienced in Physical Design and Static Timing Analysis.
  • Strong background in VLSI and Integrated Circuits.
  • Proficient in multiple design verification methodologies.
Stackforce AI infers this person is a VLSI Design Engineer with expertise in Physical Design and Timing Analysis.

Contact

LinkedIn

Skills

Core Skills

Physical DesignStatic Timing Analysis

Other Skills

Layout DesignLogic DesignTiming ClosureFloorplanningDesign Rule Checking (DRC)Layout Versus Schematic (LVS)Integrated Circuits (IC)CMOSVery-Large-Scale Integration (VLSI)LinuxPerlApplication-Specific Integrated Circuits (ASIC)

Experience

9 yrs 5 mos
Total Experience
2 yrs 4 mos
Average Tenure
3 yrs 9 mos
Current Experience

Intel corporation

Physical Design Engineer

Jul 2022 – Present · 3 yrs 9 mos · Bengaluru, Karnataka, India

Layout DesignLogic DesignPhysical DesignStatic Timing AnalysisTiming ClosureFloorplanning+8

Cadence design systems

Lead Solutions Engineer

Jun 2018 – Jun 2022 · 4 yrs · Bengaluru, Karnataka, India

Rv-vlsi vlsi and embedded systems design center

Trainee

Oct 2017 – May 2018 · 7 mos · Bengaluru, Karnataka, India

College of engineering, cherthala

Assistant Professor

Oct 2015 – Nov 2016 · 1 yr 1 mo · Alappuzha, Kerala, India

Education

Mar Athanasius College of Engineerng (MACE)

Mtech — VLSI and EMBEDDED SYSTEMS

Jan 2012 – Jan 2014

M.KUMARASAMY COLLEGE OF ENGINEERING, KARUR

Bachelor of Engineering - BE — Electronics and Communication Engineering

Jan 2008 – Jan 2012

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