DIVYA SETHI — Software Engineer

Trained fresher in VLSI Physical Design and actively looking for a job in this domain. Core competancy: • Hands-on experience on Synopsys ICC2 and Primetime. • Knowledge of complete ASIC flow and Physical Design Flow. • Proficient knowledge on Physical Design concepts: floorplan, power plan, timing driven placement, clock tree synthesis, routing and physical verification. • Hands on experience in Floorplanning and Power Planning of a block in order to meet the IR drop, clearing the floating errors and global routing congestion. • Knowledge of STA concepts like fixing setup and hold violations, timing analysis of latches, GBA, PBA, MCMM, OCV, CRPR. • Understanding of timing report analysis after each stage of APR flow. • Building CTS and knowing the effects of clock skew on timing. • Routing the design considering signal integrity and making DRC, LVS clean and also DFM analysis. • Able to write TCL and Perl scripts for automation and flow development within the team..

Stackforce AI infers this person is a VLSI Design Engineer with expertise in Physical Design and Static Timing Analysis.

Location: Bengaluru, Karnataka, India

Experience: 4 yrs 9 mos