Shaleen Agarwal

Software Engineer

Bengaluru, Karnataka, India1 yr 11 mos experience

Key Highlights

  • Proficient in SystemVerilog and Digital IC Design.
  • Strong background in Functional Verification and Debugging.
  • Experience in VLSI and digital design methodologies.
Stackforce AI infers this person is a VLSI design engineer with expertise in digital verification and debugging.

Contact

LinkedIn

Skills

Core Skills

Digital Ic DesignFunctional VerificationDebugging

Other Skills

SystemVerilogDigital DesignsProblem SolvingVery-Large-Scale Integration (VLSI)Python (Programming Language)C (Programming Language)DFTDigital logic designUniversal Verification Methodology (UVM)Verilog

Experience

1 yr 11 mos
Total Experience
1 yr 11 mos
Average Tenure
1 yr 11 mos
Current Experience

Amd

2 roles

IP Verification Engineer

Promoted

May 2024 – Present · 1 yr 11 mos · Bengaluru, Karnataka, India · On-site

  • SDE 2
SystemVerilogDigital DesignsDigital IC DesignFunctional Verification

IP Verification Engineer

May 2023 – Apr 2024 · 11 mos · Bengaluru, Karnataka, India · On-site

SystemVerilogDebuggingFunctional Verification

Verzeo

Campus Ambassador

May 2020 – Jul 2020 · 2 mos · India

Embibe

Content Editor

Apr 2020 – May 2020 · 1 mo · Rajasthan, India

Verzeo

Internet of Things Intern

Jan 2020 – Feb 2020 · 1 mo

  • Iot using arduino

Education

Indian Institute of Information Technology Design & Manufacturing Kancheepuram

Bachelor's degree — Electronic and Communications Engineering and VLSI

Jan 2019 – Jan 2024

N.K. public school

High School Diploma — science and mathematics

Jan 2004 – Jan 2018

Resonance Eduventures Limited

coaching — jee advance and mains

Jan 2018 – Jan 2019

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