Rahul Tiwari

Product Engineer

Delhi, India6 yrs 3 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

4+ years in high-performance analog and RF layout design.
Expertise in advanced layout techniques and physical verification.
Hands-on experience with advanced process nodes including FinFET.

Stackforce AI infers this person is a VLSI and Analog Design Engineer with expertise in RF and high-performance CMOS technologies.

Contact

rahul19190@iiitd.ac.in LinkedIn

Skills

Core Skills

Analog Design MethodologyCadence VirtuosoAnalog Layout Design

Other Skills

PcellIndependent ContributorRtl to gds flowElectronic CircuitsRF & Microwave DesignTestchipsParasitic ExtractionLayout Versus Schematic (LVS)PDKSystemVerilogUniversal Verification Methodology (UVM)System cVery-Large-Scale Integration (VLSI)CJava script

About

🔹 Analog Layout / PDK Engineer | RF & High-Performance CMOS | Cadence Virtuoso 🔹I am an Analog Layout / PDK Engineer with 4+ years of experience in designing high-performance analog and RF layouts for advanced CMOS technologies. Currently working at Intel, I focus on delivering silicon-proven designs used in mass production. My expertise lies in: • Analog & RF layout design (varactors, transistors, test structures) • Advanced layout techniques: common-centroid, matching, symmetry, shielding • Full physical verification flow: DRC, LVS, parasitic extraction, and S-parameter simulations • PCell development and layout automation using Cadence Virtuoso • Floorplanning, routing, and scalable testchip infrastructure I have hands-on experience working across advanced process nodes (including FinFET) and collaborating with global design and technology teams to deliver robust and reliable silicon.