Saagar S Jadhav — Software Engineer

Passionate engineer with rich experience in ASIC Validation and Logic Verification. Contributed to the validation/verification of multidimensional designs involving of complex integrated circuits. In-depth knowledge of Verilog, System Verilog, UVM methodology, enforcing test case, SOC and IP level simulation, IP level Emulation and verification. Technical leadership in the areas of micro-architecture verification, and verification methodology / tools / flows. Highly motivated team player with excellent problem-solving and communication skills. • Passionately driven Graphics Hardware Engineer with experience in Design Verification • Extensive experience in Test Bench development for IP level, use of emulation platform with FPGA Tools to accelerate simulation performance • Profound knowledge of enforcing test case, SOC and IP level simulation, IP level Emulation and verification • Skilled in writing test plans, debugging complex issues in RTL and Gate-Level netlist • Solid experience in developing the UVM based testbench from scratch • Significant exposure to pre silicon validation/emulation (Veloce, Zebu)

Stackforce AI infers this person is a Semiconductor Verification Engineer with extensive experience in ASIC and IP verification.

Location: Bengaluru, Karnataka, India

Experience: 10 yrs