Manjunatha K N — Software Engineer

Physical Design Engineer: Role: Design-Import, sanity Checks, Floor plan, Power plan, Placement, Timing optimization, CTS, Routing, timing Analysis, LVS&DRC Responsibilities: • Imported verilog netlist, read SDC, TLU+ file and linked physical library • Performed sanity checks • Floor plan: Estimate the area of the chip and aspect ratio, Placed macros and fixed macros, created the keep out margin & blockages over macros, Pin placement was done with help of guidelines given by top level, derived PG connection. • Placement: Assigning correct position to standard cells on the chip with no overlapping, applied various strategies to control congestion • CTS: Built the clock tree by using inverters and buffers for balancing skew. • Routing: In this connect all the cells physically with the metal straps • RC Extraction and Fixed trans, cap and timing violation in PRIMETIME.

Stackforce AI infers this person is a Physical Design Engineer in the Semiconductor industry.

Location: Bengaluru, Karnataka, India

Experience: 4 yrs