VINYAS J SHETTY — Software Engineer
* Well-versed with ASIC design flow (RTL to GDSII). * Designing a effective Floorplan and Powerplan with voltage drop at a desirable limit. * Comprehensive knowledge in congestion analysis and removal. * Profound knowledge in Static Timing Analysis, interpreting and analyzing the timing reports at various path groups and fixing timing violations. * Proficient knowledge in CRPR, effects of skew and inducing of multicycle path for a violation free path. * Hands on experience with Synopsys ICC and Synopsys PrimeTime tools. * Hands on experience in Linux commands and perl scripting. * Ability to analyze and customize TCL scripts to automate various PD tasks. * Ability to perform various SignOff checks.
Stackforce AI infers this person is a VLSI Design Engineer specializing in ASIC development and Physical Design.
Location: Bengaluru, Karnataka, India
Experience: 4 yrs 11 mos
Skills
- Physical Design
- Static Timing Analysis
Career Highlights
- Expert in ASIC design flow from RTL to GDSII.
- Proficient in Static Timing Analysis and timing violation resolution.
- Hands-on experience with Synopsys tools for Physical Design.
Work Experience
MediaTek
Senior Engineer (5 mos)
Engineer (4 yrs 6 mos)
Education
Advanced Diploma in ASIC Design - Physical Design at RV-VLSI Design Center
Bachelor of Engineering at Dayananda Sagar College of Engineering, BANGALORE
PUC at Vivekananda PU College
