Shalini Singh — Software Engineer

projects - 1) Decimation Clock Domain Crossing Design TOP LEVEL Details : Dealing with different clock domain frequency, need to send data from 192 MHz frequency to 12 MHz frequency then to 3 MHz frequency device client location: SONY JAPAN (offsite) skills: Digital microarchitecture, verilog, system verilog, functional coverage, assertion, sta 2)Digital FIR Filter Design Details: converting 12MHz frequency into 3MHz frequency by using FIR client location : SONY JAPAN (offsite) skills:verilog, system verilog, assertion, coverage, static timing analysis 3)Digital CIC FILTERS DESIGN Details: Filter converting 192 MHz to 12MHz client location: SONY JAPAN (offsite) skills: verilog, system verilog, assertion, coverage, Static timing analysis 4)IMAGE SENSING CAMERA DESIGN 8 MEGA PIXELS Details :12 Bit DEFECTS PIXELS CORRECTION client: Integrated Device Technology JAPAN skills: verilog, system verilog, assertion, coverage, Static timing analysis 5)AHB2APB Bridge IP Core Verification Details:HVL: System Verilog TB Methodology: UVM EDA Tool: Riviera Pro - Aldec Description: The AHB to APB bridge is an AHB slave which works as an interface between the high speed AHB and the low performance APB buses. - Architected the class based verification environment in UVM. - Defined Verification Plan - Verified the RTL module with UVM Test Bench with different test scenarios like single READ, WRITE & Burst READ, WRITE with different burst lengths. - Generated functional and code coverage for the RTL verification sign-off. Responsibilities: - Architected the class based verification environment in UVM. - Defined Verification Plan - Verified the RTL module with UVM Test Bench with different test scenarios like single READ, WRITE & Burst READ, WRITE with different burst lengths. - Generated functional and code coverage for the RTL verification sign-off. 6) Router 1x3 - RTL design and Verification Details:Router 1x3 - RTL design and Verification HDL: Verilog HVL: SystemVerilog TB Methodology: UVM EDA Tools: Questasim and ISE Description: The router accepts data packets on a single 8-bit port and routes them to one of the three output channels, channel0, channel1 and channel2.

Stackforce AI infers this person is a highly skilled engineer in digital design and verification within the semiconductor industry.

Location: Bengaluru, Karnataka, India

Experience: 7 yrs 4 mos