Feb 2022 – Present · 4 yrs 3 mos · India

Jul 2017 – Present · 8 yrs 10 mos · Bangalore

Jul 2016 – Dec 2016 · 5 mos · Bangalore, Karnataka.

• Implemented Low Power Reduction Techniques and optimized the RTL code using different libraries, cells and combinational logic.
• Integrated several sub-modules for one of the IP (Intellectual Property) of the main project and verified it's functionality.
• Generated Power Reports and Power Numbers and reiterated the steps to reduce the power consumption to fit the power budget.
• Worked on various Softwares such as Power Artist, SpyGlass which helped to check lint checks, equivalence checks to ensure overall consistency of the circuit under test.
• Automated various repetitive steps with the help of shell scripting.
• Language Used: Verilog, VHDL.

May 2015 – Jul 2015 · 2 mos · Tirora, Mahatashtra.

• Designed and presented different alternatives to improve the working efficiency of generators as the Final Project.
• Worked on Programmable Logic Circuit which relayed the functioning of different Generators which were used in the Thermal Plant.