Gunjan Malik

Software Engineer

Rohtak, Haryana, India6 yrs experience
Most Likely To Switch

Key Highlights

  • Experienced in Universal Verification Methodology and Verilog.
  • Strong foundation in Systems Engineering and programming languages.
  • Hands-on experience in design verification at MediaTek.
Stackforce AI infers this person is a skilled design verification engineer in the semiconductor industry.

Contact

LinkedIn

Skills

Core Skills

Universal Verification Methodology (uvm)Verilog

Other Skills

C (Programming Language)SystemVerilogSystems EngineeringC++PL/SQLDatabase Management System (DBMS)HTML5Cascading Style Sheets (CSS)AngularJSMATLAB

Experience

6 yrs
Total Experience
2 yrs
Average Tenure
2 yrs 10 mos
Current Experience

Mediatek

2 roles

Senior Design Verification Engineer

Jul 2023 – Present · 2 yrs 10 mos · Bengaluru, Karnataka, India · On-site

VerilogUniversal Verification Methodology (UVM)

Intern

Jan 2023 – Jun 2023 · 5 mos · Bengaluru, Karnataka, India · On-site

C (Programming Language)Verilog

Bits pilani, hyderabad campus

Teaching Assistant

Sep 2021 – Jan 2023 · 1 yr 4 mos

Tata consultancy services

Assistant System Engineer

Nov 2018 – Sep 2020 · 1 yr 10 mos · Delhi

Education

BITS Pilani, Hyderabad Campus

Master of Engineering - MEng

Bharati vidyapeeth college of engineering,new delhi

Jan 2014 – Jan 2018

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