Vidhan Singh

Software Engineer

Ayodhya, Uttar Pradesh, India5 yrs 8 mos experience

Highly Stable

Key Highlights

Senior Silicon Design Engineer with AMD experience.
Expertise in Physical Design and Unified Power Format.
Strong background in low power verification.

Stackforce AI infers this person is a Physical Design Engineer with expertise in semiconductor design and verification.

Contact

Skills

Core Skills

Physical DesignPlace & RouteUnified Power Format (upf)

Other Skills

VCLPPDNPrimetimeTiming ClosureTCL scriptingstatic low power verificationProgrammingScriptingVerilogPerlfull chip layoutPerl AutomationTimingStatic Timing AnalysisLow-power Design

About

Working as physical design engineer at intel

Experience

5 yrs 8 mos

Total Experience

3 yrs 6 mos

Average Tenure

2 yrs 1 mo

Current Experience

Amd

Senior Silicon Design Engineer

Mar 2024 – Present · 2 yrs 1 mo · Bengaluru, Karnataka, India · Hybrid

Physical Design Engineer

Physical DesignPlace & Route

Intel corporation

2 roles

Physical Design Engineer

Aug 2020 – Mar 2024 · 3 yrs 7 mos · India · Hybrid

Physical Design Engineer

Physical DesignUnified Power Format (UPF)

Intern

Jul 2019 – Jun 2020 · 11 mos · Bengaluru Area, India

Worked as signoff owner for static low power verification

Unified Power Format (UPF)

Education

Vellore Institute of Technology

Master of Technology - MTech — Vlsi Design

Jan 2018 – Jan 2020

Savitribai Phule Pune University

Bachelor of Engineering - BE — electronics and telecommunications engineering

Jan 2013 – Jan 2017

Stackforce found 100+ more professionals with Physical Design & Place & Route

Explore similar profiles based on matching skills and experience

Abhishek Maurya

Physical Design Engineer

at Intel Corporation

Bengaluru, India5 yrs 7 mos exp

Static Timing AnalysisECO tool

Bathula Narendra Reddy

Member of Technical Staff

at AMD

India10 yrs exp

PNRFormal Verification

Lochan Anil Vyas

Member of Technical Staff

at AMD

Bengaluru, India11 yrs 5 mos exp

Power OptimizationSystem on a Chip (SoC)Physical DesignLibrary Preparation

Niraj Mohan Nambiar

EDA Tools Hardware Engineer

at Intel Corporation

Bengaluru, India4 yrs 10 mos exp

Electronic Engineering

sambit datta

SOC Full Chip Floorplanning and Physical Integration lead

at Intel Corporation

Bengaluru, India14 yrs 9 mos exp

Physical DesignSystem on a Chip (SoC)

Yash Gaud

CPU Physical Design Engineer

at Intel Corporation

Bengaluru, India8 yrs 11 mos exp

Physical DesignVLSI

Hariharan M V

Senior Silicon Design Engineer

at AMD

Bangalore Urban, India6 yrs 9 mos exp

Physical DesignStatic Timing Analysis

Adarsha A

Senior FPGA R&D Engineer

at Logic Fruit Technologies

Bengaluru, India8 yrs 6 mos exp

Field-Programmable Gate Arrays (FPGA)Documentation