Abhishek Maurya

Product Engineer

Bengaluru, Karnataka, India5 yrs 7 mos experience

AI ML PractitionerAI Enabled

Key Highlights

Led AI/ML initiatives to improve ECO tool performance.
Expert in Static Timing Analysis and ECO processes.
Master's degree in VLSI and Embedded Systems.

Stackforce AI infers this person is a Semiconductor Engineering professional with a focus on physical design and automation.

Contact

Skills

Core Skills

Static Timing AnalysisEco Tool

Other Skills

Design FlowRTL DesignAI/MLUnified Power Format (UPF)Synopsys PrimetimePower AnalysisDigital DesignsIntegrated Circuits (IC)Electronic EngineeringPlace & RouteTimingDesign qualitySystem on a Chip (SoC)VerilogVery-Large-Scale Integration (VLSI)

About

At Intel Corporation, contributed as the Global Flow Owner for the ECO tool, ensuring efficient deployment and continuous improvements. Worked on implementing advanced features such as Two-Pass Leakage Recovery and Vmin Robustness Design Variation Analysis, while serving as the Point of Contact for Static Timing Analysis and timing ECO across multiple projects. Led AI/ML-driven initiatives to enhance Turnaround Time (TAT) and Quality of Results (QoR) in the ECO domain. Completed a Master of Technology in VLSI and Embedded Systems from DIAT, DRDO, where coursework and projects sharpened expertise in Unified Power Format (UPF), Synopsys Primetime, and Power Analysis. A passion for innovation and problem-solving drives contributions to cutting-edge advancements in physical design and automation.

Experience

5 yrs 7 mos

Total Experience

5 yrs 7 mos

Average Tenure

5 yrs 7 mos

Current Experience

Intel corporation

2 roles

Physical Design Engineer

Jun 2021 – Present · 4 yrs 10 mos · Bengaluru, Karnataka, India

As the Global Flow Owner for the ECO tool, I've successfully released and continuous improvement initiatives over the past three years.
Driven the implementation of advanced ECO features including Two-Pass Leakage Recovery, Vmin Robustness Design Variation Analysis, IR ECO, Metal ECO, and BEOL, etc.
Serving as the Point of Contact for Static Timing Analysis and timing ECO across various projects, Ensured efficient deployment and adherence to project timelines.
Spearheaded the development of new ECO tool flows. Leveraged AI/ML to enhance Turnaround Time (TAT) and Quality of Results (QoR) within the ECO domain.

Design FlowRTL DesignStatic Timing AnalysisECO toolAI/ML

Intern

Aug 2020 – May 2021 · 9 mos · Bengaluru, Karnataka, India

Responsible for spearheading the development of the LV (Layout Verification) flow, focusing on enhancing Turnaround Time (TAT) and computation efficiency.
Conducted comprehensive Tool Validation procedures prior to project deployment.
Acquired in depth understanding of all major LV rules to ensure thorough compliance and optimization.