Chandan Kumar

Software Engineer

Delhi, India5 yrs 11 mos experience

Key Highlights

Expert in RTL design and FPGA development.
Experience with PCIe protocols and 5G baseband processing.
Proficient in Static Timing Analysis and digital system optimization.

Stackforce AI infers this person is a Telecommunications Engineer specializing in FPGA and digital design.

Contact

Skills

Core Skills

Rtl DesignFpgaPcieDigital Signal Processing

Other Skills

Static Timing Analysis5G New Radio (NR)Field-Programmable Gate Arrays (FPGA)FPGA prototypingModulationDemodulationVerilogRTL CodingRTL SimulationHigh-speed Digital DesignLifiGNU OctaveRTL DevelopmentModelSimQuestaSim

About

As a Digital Design Engineer, I specialize in RTL design, FPGA development, and Static Timing Analysis (STA). My expertise includes PCIe protocols, 5G baseband processing, and Visible Light Communication (VLC), with experience in designing high-performance digital systems. I have worked on various FPGAs, including Xilinx ZCU102 and Intel Arria10, and have used tools like Vivado, Quartus Prime, and Lattice Radiant. Passionate about optimizing digital designs for efficiency and performance, I am open to opportunities in RTL design, FPGA-based systems, and STA optimization.

Experience

5 yrs 11 mos

Total Experience

1 yr 7 mos

Average Tenure

1 yr

Current Experience

Ibm

Logic Design Engineer

Apr 2025 – Present · 1 yr

Signaltron

Digital Design Engineer

Jun 2023 – Mar 2025 · 1 yr 9 mos · Bengaluru, Karnataka, India

PCIe Gen3 x4 System Design
Designed the architecture for a PCIe-based data transfer system using PCIe Gen3 x4.
Developed PCIe PIO (Programmed I/O) for the Endpoint (EP) on FPGA, enabling data transfer between a server and an FPGA over a PCIe link.
Conducted simulation, synthesis, and timing analysis to ensure functional correctness and optimal performance of PIO.
5G gNB Chip Design(RTL)
Developed critical components for the 5G baseband processing, including Channel State Information Reference Signal (CSI-RS), Physical Downlink Shared Channel (PDSCH), Demodulation Reference Signal (DMRS), and Beamforming modules.
FPGA-based ORU Project
Developed a testbench to validate the functionality of the RTL for the PRACH module of the ORU project.

Static Timing AnalysisRTL DesignPCIe5G New Radio (NR)FPGA

Photonics lab - iit delhi

Mtech research

May 2022 – May 2023 · 1 yr · Delhi, India

Modulation and demodulation in Visible light communication system using FPGA
Implemented a 4-PAM modulator and demodulator module to enhance the data rate of the LiFi transmitter using the Xilinx (ZCU-102) FPGA and FMC-150 (ADC/DAC)
Implemented the Manchester and the VOOK modulator and demodulator module in using the Xilinx Arty-A7-35T FPGA to mitigate flickering and to provide dimming support in the LiFi transmitter.

Field-Programmable Gate Arrays (FPGA)FPGA prototypingModulationDemodulationFPGADigital Signal Processing