Mohd Adil Khan — DevOps Engineer

• Currently having around 15+ years of experience in various phases of ASIC design & verification. • Excellent technical expertise with interpersonal skills while interacting with the customers across the globe. • Experience in using Industry Standard EDA Tools for Front-End Design & fluent in using Verilog & System Verilog for RTL Coding and development of Verification Environment components. • Exposure in working with complex SoCs/IPs at various stage of the flow based on PCI-Express protocol, PCI-Express IOV, UCIE, ETHERNET, USB, AXI. • Hands-on Experience in ASIC Design & Verification Flows. • Knowledge of scripting language “PERL”. • Experience on tools like Modelsim, Leonardo Spectrum, VCS, and Questa Sim. • Module Verification: Experience in creation of various parts of test-bench using System Verilog, Testing/Debugging, Coverage generation and analysis, SV Assertions. Specialties: 1. ASIC Front End Design & Verification. 2. Development of IP/SOC Level verification Environment. 3. Hands-on Exp in Verilog, System Verilog, C++, OVM/UVM.

Stackforce AI infers this person is a VLSI design and verification expert with extensive experience in ASIC and SoC development.

Location: Noida, Uttar Pradesh, India

Experience: 17 yrs 3 mos