Joal P Jose — Software Engineer

As a Senior FPGA Design Engineer at Qi-Cap, I specialise in developing ultra-low-latency and highly efficient hardware solutions tailored for high-frequency trading systems. My expertise spans FPGA architecture, microarchitecture design, and comprehensive verification using SystemVerilog and the Universal Verification Methodology (UVM), with a strong focus on robustness and performance. I lead end-to-end design efforts including architecture definition, feature implementation, and RTL coding, complemented by verification framework development from scratch. I pioneered automation of UVM testbench generation scripts to accelerate verification cycles, allowing teams to focus on functional coverage rather than the framework. My experience includes optimising order book trading system designs by addressing latency bottlenecks, re-architecting core components for resource efficiency, integrating advanced memory solutions like High Bandwidth Memory (HBM), and implementing multi-link scalable communication cores. I have delivered hardware acceleration of cryptographic functions such as MD5 with dynamic control and latency optimisations. In addition, I develop FPGA-based Network Interface Cards (NICs) enabling real-time processing of exchange data through PCIe, integrating complex protocol handling and hybrid solutions. I am proficient in Xilinx Vivado, Cadence Xcelium, SimVision, HAL, and have applied High-Level Synthesis (HLS) for rapid prototyping to explore design alternatives quickly. My work balances cutting-edge innovation with practical improvements in timing closure and system reliability, delivering solutions that meet the demanding performance and scalability requirements of modern trading infrastructure.

Stackforce AI infers this person is a Fintech FPGA Design Engineer specializing in ultra-low-latency hardware solutions.

Location: Bengaluru, Karnataka, India

Experience: 5 yrs 2 mos

Skills

Fpga Design
Architecture
Design Verification
Uvm
Hls

Career Highlights

Pioneered automation of UVM testbench generation scripts.
Delivered hardware acceleration of cryptographic functions.
Optimized order book trading system designs for latency.

Work Experience

QiCAP.Ai

Senior Design Engineer (3 yrs 11 mos)

Member Technical Staff (7 mos)

Acceletrade

Intern (8 mos)

Maven Silicon

Intern (2 mos)

Trainee (1 yr 6 mos)

Education

Bachelor of Engineering - BE at Cambridge Institute of Technology

Pre-University at St Claret Comp PU College

SSLC at Schoenstatt St. Marys High School

Joal P Jose

Software Engineer

Bengaluru, Karnataka, India5 yrs 2 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

Pioneered automation of UVM testbench generation scripts.
Delivered hardware acceleration of cryptographic functions.
Optimized order book trading system designs for latency.

Stackforce AI infers this person is a Fintech FPGA Design Engineer specializing in ultra-low-latency hardware solutions.

Contact

Skills

Core Skills

Fpga DesignArchitectureDesign VerificationUvmHls

Other Skills

AMBAAXIAXI LiteAssertion Based VerificationC (Programming Language)C/C++Constraint Random VerificationFPGAHigh Bandwidth MemoryLinux Command LineMD5Market Book/ Order BookMicroarchitectureOptimizationPCIe

About

Experience

Qicap.ai

2 roles

Senior Design Engineer

Promoted

Apr 2022 – Present · 3 yrs 11 mos · Bengaluru, Karnataka, India · On-site

Identified and resolved architectural bottlenecks in the order book replacing multicycle operations with single-cycle logic for faster performance and integrated High Bandwidth Memory to meet large memory capacity demands enabling support for complex data-intensive workloads
Re-architected the order book to overcome core system constraints by shifting from a fixed to a moving window design. simplifying resource usage, and parallelising key modules. Doubled system clock frequency for further latency reduction, introduced lookahead logic to transmit uncrossed book levels and benchmarked the optimised design cutting latency from microseconds to nanoseconds and dramatically improving processing speed
Integrated MD5 computation into hardware by designing custom packet creation logic and enabling dynamic, realtime toggling of MD5 functionality. Improved flexibility by allowing ondemand hardware MD5 activation or deactivation. Proposed and applied latency optimisations using multicycle path constraints, delivering a proof-of-concept that demonstrated reduced computation delay and enhanced performance
Refactored and optimised multiple hardware modules by removing redundant logic and adopting superior IP blocks for greater clarity and maintainability. Enhanced architectural coherence and following analysis, recommended reducing AXI path frequency in non-latency-critical sections to ease timing closure culminating in improved timing margins and overall design robustness
Added scalable support for 1 to 4 CTCL by creating a modular core decoupled from legacy dependencies. Expanded design with multiorder type and multiclient handling. Proposed PCIe packet combination to reduce packet count minimise processing steps and simplify data flow improving overall system efficiency
Developed an FPGA-based NIC to receive and transmit UDP data. Added support for filtered feed and order book transmission. Integrated an orthogonal hybrid solution into the design to enhance functionality

FPGAHigh Bandwidth MemoryAXIMD5PCIeFPGA Design+1

Member Technical Staff

Aug 2021 – Mar 2022 · 7 mos · Bengaluru, Karnataka, India · On-site

Developed comprehensive UVM-based testbench for order book module, analyzing system architecture and block-level functionality while creating complete verification framework from scratch including drivers, monitors, sequencers, and scoreboards for DUT, constrained random verification to maximize coverage, and systematic reporting of identified RTL bugs to design team.
Proposed automated UVM testbench generation script for company transition from basic Verilog to UVM-based verification methodology, streamlining verification workflow by enabling rapid testbench creation and allowing engineering teams to focus on logic validation rather than structural setup.
Led complete RTL implementation of order book trading system across multiple interconnected modules after demonstrating comprehensive understanding of system architecture, consolidating expertise in high-frequency trading design and ultra-low latency hardware principles.

UVMRTLVerification FrameworkDesign Verification

Acceletrade

Intern

Nov 2020 – Jul 2021 · 8 mos · Bengaluru, Karnataka, India · Remote

Evaluated Vivado HLS tool for automated C/C++/SystemC to RTL conversion, analyzing block-level interface protocols (ap_start, ap_idle, ap_done) and identifying C/C++ coding limitations such as dynamic memory allocation constraints for hardware synthesis.
Applied pragma directive optimization techniques including loop pipelining, loop unrolling, and parallel execution directives to transform sequential C++ code into optimized parallel hardware implementations and studied latency metrics for hardware acceleration methodologies.
Developed and integrated a functional HLS-based proof-of-concept module into existing FPGA systems, validating toolchain compatibility, accelerating development timelines, and gaining expertise in HLS-to-RTL conversion methodologies and hardware synthesis flows.

Vivado HLSC/C++RTL ConversionHLSFPGA Design

Maven silicon

2 roles

Intern

Nov 2019 – Jan 2020 · 2 mos · Bengaluru, Karnataka, India

Trainee

May 2019 – Nov 2020 · 1 yr 6 mos · Bengaluru, Karnataka, India

Completed comprehensive SystemVerilog verification training covering advanced language constructs including datatypes, dynamic arrays, queues, associative arrays, and object-oriented programming concepts for robust testbench development.
Mastered Universal Verification Methodology (UVM) framework implementation including verification components, sequence items, sequencers, drivers, monitors, scoreboards, and factory patterns for scalable and reusable verification environments.
Applied advanced SystemVerilog features including interfaces, clocking blocks, modports, fork-join constructs, mailboxes, constraints, and functional coverage to create comprehensive DUT validation testbenches.
Strengthened theoretical understanding through hands-on laboratory exercises and practical verification projects, developing expertise in transaction-level modeling and constrained random testing methodologies.

SystemVerilogUVMDesign Verification