Anupam Das

Software Engineer

Bengaluru, Karnataka, India8 yrs 7 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

Over 9 years of experience in semiconductor industry.
Expertise in DFT Verification and project leadership.
Proficient in cutting-edge semiconductor chip design.

Stackforce AI infers this person is a semiconductor industry expert with a focus on DFT and ASIC design.

Contact

Skills

Core Skills

DftAsic DesignTest AutomationFunctional VerificationVlsiLeadership

Other Skills

CMicrosoft ExcelMBISTTeamworkUFSDigital Circuit DesignAutomatic Test Pattern Generation (ATPG)Microsoft PowerPointLinuxField-Programmable Gate Arrays (FPGA)TCLPerlRTL DesignSystemVerilogRTL Verification

About

As a Senior ASIC Engineer with more than 9 years of experience in the semiconductor industry, I possess expertise in both DFT Verification and project leadership. I am highly skilled in Verilog, Perl, System Verilog, ATPG, Clock Verif, Testplan Design, Soc Verif, Linux, Perforce, In System Testing, and Silicon Debug, among other industry-standard methodologies and tools. My track record of leading successful verification projects and teams showcases my proficiency in cutting-edge semiconductor chip design and implementation. With a Bachelor of Technology (B.Tech.) in Electrical and Electronics Engineering from the National Institute of Technology Tiruchirappalli, I am well-equipped to contribute significantly as an experienced DFT/IST Design verification lead in the industry.

Experience

8 yrs 7 mos

Total Experience

4 yrs 3 mos

Average Tenure

7 yrs

Current Experience

Nvidia

2 roles

Senior ASIC Engineer - DFT/IST at NVIDIA

Promoted

Jun 2022 – Present · 3 yrs 10 mos

Leading the Pre-Silicon and Post Silicon In-System Test (IST) verification of next-generation high-performance SOC designs, with a focus on meeting ASIL (ISO 26262) requirements. Specifically, verified custom DFT (Design For Test) features, clocks, scan isolation, and IST backbone (PCIe/UFS/eMMC), as well as microarchitecture and logic. Developed and executed verification test plans at different levels of design hierarchy, including super unit and full chip environments, utilizing the latest simulation technologies, such as PAV, XPROP, and regular simulation. Developed testbench components, including stimulus drivers, monitors, and checkers. Identified design bugs and worked with RTL/Arch owners to resolve all failures and discrepancies. Participated in technical reviews of specifications, designs, and test plans, and identified areas of concern to meet design quality objectives. Managed the assignment and execution of verification tasks with a small team of verification engineers.

DFTCMicrosoft ExcelLeadershipASIC DesignMBIST+22

DFT Engineer

Apr 2019 – Jun 2022 · 3 yrs 2 mos

Work focused on DFT verification for high-performance GPU, automotive, and CPU chips at the super unit and SOC levels, with a particular emphasis on ASIL-D compliance. I specialize in verifying DFX logic, DFX clock, LBIST/MBIST, JTAG, IJTAG, Uphy clocking, and SSN. Additionally, I am involved in both pre- and post-silicon debug and bringup. My responsibilities include verifying the test plan, performing in system tests, and managing verification task assignments for a team of engineers. I stay up-to-date on the latest simulation technologies, such as PAV and XPROP, and develop testbench components, including stimulus drivers, monitors, and checkers, to find and resolve design bugs.

DFTCMicrosoft ExcelASIC DesignMBISTTeamwork+17

Schneider electric

2 roles

Test Automation Engineer

Apr 2018 – Mar 2019 · 11 mos

Part of Intelligent Electronic device team of Schneider Electric R&D department as a
Verification Engineer. My role was to automate test-cases using python, selenium and pymodbus for Ethernet gateways which also interacted with MODBUS protocol and web-services .

Microsoft ExcelTeamworkMicrosoft PowerPointTest AutomationPythonFunctional Verification+3

Graduate Engineering Trainee

Jul 2017 – Mar 2018 · 8 mos

Part of Intelligent Electronic device team of Schneider Electric R&D department as a GET. Worked on verification of various devices (Ethernet gateways, HMI, Modbus slaves), its interface’s and the protocols it uses. My role was writing test cases, performing system level test on devices and cloud services, performing regression and manual testing on devices.

Microsoft ExcelTeamworkMicrosoft PowerPointTest AutomationPythonFunctional Verification+2

International institute of information technology bangalore

Summer Research Intern

Jun 2016 – Jul 2016 · 1 mo · Bangalore

Worked on a project to design and implement the SAR based All Digital Phase locked loop for dynamic frequency scaling in processors under Dr.Subajit Sen IIIT-B. The project work involved replacing the conventional ADPLL with SAR based approach with a Bang-Bang Phase Detector for faster lock. My role was to design and code the whole block in VHDL in Quartus Platform and implement it on DE0-Nano FPGA Board.

Microsoft ExcelMicrosoft PowerPointVLSIMicrosoft OfficeVerilogDebugging

Indian institute of technology, guwahati

Summer Research Intern

May 2015 – Jul 2015 · 2 mos · Guwahati

Worked on a project to design and implement the Galois Field Multiplier using Programmable Cellular Automata for the AES cryptographic algorithm under Dr. Shaikh Rafi Ahmed IIT-G. The project work involved replacing the conventional GF multiplier with a PCA-based multiplier and to introduce pipelining in the process so that a tradeoff could be reached between power and throughput of the AES in GCM mode. My role was to design and code the multiplier in MATLAB as well as in Verilog

Microsoft ExcelMicrosoft PowerPointVLSIMicrosoft OfficeVerilogDebugging

Pragyan - nit trichy's technical fest

Event Manager

Mar 2015 – Mar 2015 · 0 mo · NIT Trichy

'Pragyan' is the annual tehno-managerial ISO certified festival of NIT, Trichy. Currently in the Events team.Responsible for conducting the event Robowars during Pragyan

Microsoft ExcelMicrosoft PowerPointMicrosoft Office

South eastern railway

Trainee

Dec 2014 – Jan 2015 · 1 mo · West Bengal, India

Underwent In-plant training at Traction and OHE Department, South Eastern Railways at Kolkata. The training involved comprehending power supply system of the railways, foundation, bonding, cantilever design, Over Head Equipment maintenance

Microsoft ExcelLeadershipTeamworkMicrosoft PowerPointTeam ManagementMicrosoft Office