Srinu Reddy

Software Engineer

Bengaluru, Karnataka, India8 yrs 6 mos experience
Highly Stable

Key Highlights

  • 4+ years in SoC physical design flow.
  • Hands-on experience in PNR flow implementation.
  • Expertise in timing closure and STA.
Stackforce AI infers this person is a VLSI Design Engineer with expertise in physical design and ASIC methodologies.

Contact

Skills

Core Skills

Timing Closure

Other Skills

STAbasics of system verilogASIC Design flowApplication-Specific Integrated Circuits (ASIC)basics of verilog coadingbasics of RTL verificationbasics of perlLow-power DesignDFTVery-Large-Scale Integration (VLSI)Logic Synthesis

About

4+ years of experience in soc physical design flow in various technology nodes. Hands on experience in implementing pnr flow of floorplan , synthesis, placement, clock tree and routing.

Experience

8 yrs 6 mos
Total Experience
6 yrs 4 mos
Average Tenure
5 yrs 7 mos
Current Experience

Intel corporation

SoC Design Engineer

Sep 2020Present · 5 yrs 7 mos · India · Hybrid

Timing ClosureSTA

Rv-vlsi vlsi and embedded systems design center

physical design engineer traine

Oct 2017Feb 2024 · 6 yrs 4 mos · banglore

Education

Annamacharya Institute of Technology & Sciences,(Autonomous) New Bowenpally, Rajampet

Master of Technology — DECS

Jan 2015Jan 2017

Jawaharlal Nehru Technological University, Anantapur

Bachelor of Technology - BTech — Electronics and Communications Engineering

Jan 2012Jan 2015

State Board of Technical Education and Training

diploma — Electroincs and communication engineering

Jan 2009Jan 2012

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