V

Venkateswara Rao Bhima

Director of Engineering

Bengaluru, Karnataka, India27 yrs 3 mos experience
Most Likely To SwitchHighly Stable

Key Highlights

  • Expert in GPU SoC product development.
  • Proven track record in chip design across multiple technologies.
  • Strong leadership in managing engineering teams.
Stackforce AI infers this person is a semiconductor design expert with extensive experience in SoC and GPU architectures.

Contact

LinkedIn

Skills

Core Skills

Soc DesignGpu ArchitectureEthernet TechnologyDesign EngineeringChip DesignLibrary Development

Other Skills

GPU SoC PD5nm technology1.8nm technologySoC PDEthernet chips45nm technology28nm technologyPlace and RouteARM113690nm technologyIR drop analysisStandard cell library development0.25u technology

Experience

27 yrs 3 mos
Total Experience
4 yrs 7 mos
Average Tenure
9 yrs 3 mos
Current Experience

Intel corporation

Senior Manager

Jan 2017 – Present · 9 yrs 3 mos · India · On-site

  • Working as GPU SoC PD lead in nodes ranging from 5nm to 1.8nm
GPU SoC PD5nm technology1.8nm technologySoC DesignGPU Architecture

Mediatek (india) pvt ltd

Principal Engineer

May 2014 – Jan 2017 · 2 yrs 8 mos · India · On-site

  • Worked as SoC PD lead for Ethernet chips in 45nm and 28nm
SoC PDEthernet chips45nm technology28nm technologySoC DesignEthernet Technology

Smartplay technologies

Manager

Jan 2007 – Jan 2014 · 7 yrs

Synopsys india pvt ltd

Sr Design enginer

Sep 2005 – May 2007 · 1 yr 8 mos

  • Worked as Senior Design Engineer in Synopsys Hyderabad from 2005 to May 2007 and involved in Place and route of ARM1136 Place and Route (90nm).Participated in Place and route of another chip(for Thompson electronics).
Place and RouteARM113690nm technologyDesign EngineeringChip Design

Alliance semiconductor

Sr Design engineer

Oct 2000 – Aug 2005 · 4 yrs 10 mos

  • Worked as Design engineer in Alliance Semiconductor Hyderabad and involved in Place and Route,floorplan and IR drop analysis of various bridge products like PCI-PCI,PCI-PCIX and PCI-HT-PCI etc
Design EngineeringPlace and RouteIR drop analysisChip Design

Spike technologies india pvt ltd

Design Engineer

May 1998 – Jul 2000 · 2 yrs 2 mos

  • Worked in Spike Technologies as Design engineer and involved in standard cell library development of various vendors like TSMC 0.25u, NEC 0.25u,TI 0.25u,AMD 0.25u etc
Standard cell library development0.25u technologyDesign EngineeringLibrary Development

Education

Andhra University

B.E — Electronics

Jan 1994 – Jan 1998

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