Amisha P

Software Engineer

Kozhikode, Kerala, India3 yrs 7 mos experience
Highly Stable

Key Highlights

  • Experienced in DFT and RTL design methodologies.
  • Proficient in Verilog and JTAG standards.
  • Strong background in silicon design engineering.
Stackforce AI infers this person is a Silicon Design Engineer with expertise in DFT and RTL methodologies.

Contact

LinkedIn

Skills

Core Skills

DftRtl ImplementationRtl Verification

Other Skills

SSNSanity checksScan InsertionATPGVerilogJoint Test Action Group (JTAG)Mbist

Experience

3 yrs 7 mos
Total Experience
3 yrs
Average Tenure
7 mos
Current Experience

Amd

Silicon Design Engineer 2 at AMD

Sep 2025 – Present · 7 mos · Bengaluru, Karnataka, India · On-site

DFTRTL VerificationRTL implementationSSNSanity checksScan Insertion+4

Insemi technology services pvt. ltd.

3 roles

Design Engineer

Promoted

Jun 2024 – Oct 2025 · 1 yr 4 mos

RTL implementationSSN

Associate Design Engineer

Promoted

Jun 2023 – Jun 2024 · 1 yr

RTL VerificationSSN

Junior DFT Engineer

Sep 2022 – Jun 2023 · 9 mos

MbistATPGDFT

Education

College of Engineering Trivandrum

Master of Technology - MTech

Nov 2020 – Aug 2022

L.B.S College of Engineering , Kasaragod

Bachelor of Technology - BTech

Aug 2016 – Jul 2020

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